Abstract: A system is provided to perform slack apportionment for an integrated circuit. The system includes a time calculation module and a slack apportion module. The time calculation module determines an arrival time corresponding to a target pin in signal communication with a signal path. The slack apportion module determines a total slack associated with the signal path and determines a slack threshold value that is equal to a portion of the total slack. The time calculation module further determines an apportioned arrival time associated with the signal path based on the arrival time and a delay offset value. The slack apportion module further determines a residual slack apportionment value based on a residual slack and the number of macros associated with the signal path. Accordingly, the time calculation module determines a modified apportioned arrival time based on the residual slack apportionment value and the apportioned arrival time.

Abstract: A system is provided to perform slack apportionment for an integrated circuit. The system includes a time calculation module and a slack apportion module. The time calculation module determines an arrival time corresponding to a target pin in signal communication with a signal path. The slack apportion module determines a total slack associated with the signal path and determines a slack threshold value that is equal to a portion of the total slack. The time calculation module further determines an apportioned arrival time associated with the signal path based on the arrival time and a delay offset value. The slack apportion module further determines a residual slack apportionment value based on a residual slack and the number of macros associated with the signal path. Accordingly, the time calculation module determines a modified apportioned arrival time based on the residual slack apportionment value and the apportioned arrival time.

Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC design, generating a blockage circuit section that represents a blockage aggressor circuit in the IC design, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Abstract: A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.

Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

Abstract: A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.

Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

Abstract: Timing window manipulation for noise reduction includes: selecting a path of a circuit design having a timing violation from a timing analysis of a victim window; determining an aggressor net coupled to a victim net along the path; determining a propagation path through the determined aggressor net; propagating a victim window value backward through the propagation path, the victim window value associated with the victim net; and modifying circuit characteristics of the circuit design within a switching window associated with the aggressor net based at least on the propagated victim window value.

Abstract: Timing window manipulation for noise reduction includes: selecting a path of a circuit design having a timing violation from a timing analysis of a victim window; determining an aggressor net coupled to a victim net along the path; determining a propagation path through the determined aggressor net; propagating a victim window value backward through the propagation path, the victim window value associated with the victim net; and modifying circuit characteristics of the circuit design within a switching window associated with the aggressor net based at least on the propagated victim window value.

Abstract: Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.

Abstract: Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.

Abstract: A data transmission system is proposed, for example for video-on-demand, internet or multimedia applications, in which a number of subscribers in a building are connected to a central server through at least in part twisted pair cables within the building. Compensation for the channel distortion caused by the use of twisted pair cables is provided by the use of pre-emphasis filters in the outgoing data lines from the server. The required coefficients for the pre-emphasis filters are established by first characterizing the distortion properties of a channel by the use of a test signal.