Patents by Inventor Tsz Yin Ho
Tsz Yin Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8513542Abstract: An integrated circuit leaded stacked package system includes forming a no-lead integrated circuit package having a mold cap, and attaching a mold cap of an extended-lead integrated circuit package facing the mold cap of the no-lead integrated circuit package.Type: GrantFiled: March 8, 2006Date of Patent: August 20, 2013Assignee: Stats Chippac Ltd.Inventors: Heap Hoe Kuan, Tsz Yin Ho, Dioscoro A. Merilo, Seng Guan Chow, Antonio B. Dimaano
-
Patent number: 8164172Abstract: An integrated circuit package in package system includes: a base integrated circuit package with a base lead substantially coplanar with a base die paddle and having a portion with a substantially planar base surface; an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface; a package-stacking layer over the base integrated circuit package; and the extended-lead integrated circuit package over the base integrated circuit package including: an end portion of the extended lead, directly on the package-stacking layer, and the extended lead exposed by and extending away from the bottom of the side of an extended-lead encapsulation and bending downwards toward the direction of the package stacking layer with the substantially planar lead-end surface coplanar with the substantially planar base surface.Type: GrantFiled: June 22, 2011Date of Patent: April 24, 2012Assignee: STATS ChipPAC Ltd.Inventors: Tsz Yin Ho, Dioscoro A. Merilo, Seng Guan Chow, Antonio B. Dimaanor, Jr., Heap Hoe Kuan
-
Publication number: 20110248411Abstract: An integrated circuit package in package system includes: a base integrated circuit package with a base lead substantially coplanar with a base die paddle and having a portion with a substantially planar base surface; an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface; a package-stacking layer over the base integrated circuit package; and the extended-lead integrated circuit package over the base integrated circuit package including: an end portion of the extended lead, directly on the package-stacking layer, and the extended lead exposed by and extending away from the bottom of the side of an extended-lead encapsulation and bending downwards toward the direction of the package stacking layer with the substantially planar lead-end surface coplanar with the substantially planar base surface.Type: ApplicationFiled: June 22, 2011Publication date: October 13, 2011Inventors: Tsz Yin Ho, Dioscoro A. Merilo, Seng Guan Chow, Antonio B. Dimaano, JR., Heap Hoe Kuan
-
Patent number: 7986043Abstract: An integrated circuit package on package system including forming an interconnect integrated circuit package and attaching an extended-lead integrated circuit package on the interconnect integrated circuit package wherein a mold cap of the extended-lead integrated circuit package faces a mold cap of the interconnect integrated circuit package.Type: GrantFiled: March 8, 2006Date of Patent: July 26, 2011Assignee: Stats Chippac Ltd.Inventors: Dioscoro A. Merilo, Seng Guan Chow, Antonio B. Dimaano, Jr., Heap Hoe Kuan, Tsz Yin Ho
-
Patent number: 7981702Abstract: An integrated circuit package in package system including forming a base integrated circuit package with a base lead having a portion with a substantially planar base surface, forming an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface, and stacking the extended-lead integrated circuit package over the base integrated circuit package with the substantially planar lead-end surface coplanar with the substantially planar base surface.Type: GrantFiled: March 8, 2006Date of Patent: July 19, 2011Assignee: Stats Chippac Ltd.Inventors: Tsz Yin Ho, Dioscoro A. Merilo, Seng Guan Chow, Antonio B. Dimaano, Jr., Heap Hoe Kuan
-
Patent number: 7928564Abstract: A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink.Type: GrantFiled: September 24, 2008Date of Patent: April 19, 2011Assignee: Stats Chippac Ltd.Inventors: Il Kwon Shim, Dario S. Filoteo, Jr., Tsz Yin Ho, Sebastian T. M. Soon
-
Patent number: 7622325Abstract: An integrated circuit package system including a high-density small footprint system-in-package with a substrate is provided. Passive components are mounted on the substrate. Solder separators are provided on the substrate, the solder separators having flattened tops at a predetermined height above the substrate. A die is supported on the solder separators above the substrate.Type: GrantFiled: October 29, 2005Date of Patent: November 24, 2009Assignee: Stats Chippac Ltd.Inventors: IL Kwon Shim, Tsz Yin Ho, Dario S. Filoteo, Jr., Seng Guan Chow
-
Patent number: 7619314Abstract: An integrated circuit package system includes providing a leadframe, forming an aperture within the leadframe, mounting an integrated circuit package over or under the aperture, and mounting a die over the integrated circuit package with the die located within the aperture.Type: GrantFiled: October 9, 2007Date of Patent: November 17, 2009Assignee: Stats Chippac Ltd.Inventors: Dario S. Filoteo, Jr., Tsz Yin Ho
-
Publication number: 20090014866Abstract: A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink.Type: ApplicationFiled: September 24, 2008Publication date: January 15, 2009Inventors: Il Kwon Shim, Dario S. Filoteo, JR., Tsz Yin Ho, Sebastian T. M. Soon
-
Patent number: 7445955Abstract: A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink.Type: GrantFiled: July 12, 2005Date of Patent: November 4, 2008Assignee: Stats Chippac Ltd.Inventors: Il Kwon Shim, Dario S Filoteo, Jr., Tsz Yin Ho, Sebastian T. M. Soon
-
Patent number: 7298038Abstract: An integrated circuit package system including a leadframe having an aperture provided therein and an integrated circuit package mounted to the leadframe over or under the aperture. A die is mounted within the aperture to the integrated circuit package and the die includes a plurality of the die.Type: GrantFiled: February 25, 2006Date of Patent: November 20, 2007Assignee: Stats Chippac Ltd.Inventors: Dario S. Filoteo, Jr., Tsz Yin Ho
-
Publication number: 20070209834Abstract: An integrated circuit leaded stacked package system including forming an no-lead integrated circuit package having a mold cap, and attaching a mold cap of an extended-lead integrated circuit package facing the mold cap of the no-lead integrated circuit package.Type: ApplicationFiled: March 8, 2006Publication date: September 13, 2007Applicant: STATS CHIPPAC LTD.Inventors: Heap Hoe Kuan, Tsz Yin Ho, Dioscoro Merilo, Seng Guan Chow, Antonio Dimaano
-
Publication number: 20070210443Abstract: An integrated circuit package on package system including forming an interconnect integrated circuit package and attaching an extended-lead integrated circuit package on the interconnect integrated circuit package wherein a mold cap of the extended-lead integrated circuit package faces a mold cap of the interconnect integrated circuit package.Type: ApplicationFiled: March 8, 2006Publication date: September 13, 2007Applicant: STATS CHIPPAC LTD.Inventors: Dioscoro Merilo, Seng Guan Chow, Antonio Dimaano, Heap Hoe Kuan, Tsz Yin Ho
-
Publication number: 20070210424Abstract: An integrated circuit package in package system including forming a base integrated circuit package with a base lead having a portion with a substantially planar base surface, forming an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface, and stacking the extended-lead integrated circuit package over the base integrated circuit package with the substantially planar lead-end surface coplanar with the substantially planar base surface.Type: ApplicationFiled: March 8, 2006Publication date: September 13, 2007Applicant: STATS CHIPPAC LTD.Inventors: Tsz Yin Ho, Dioscoro Merilo, Seng Guan Chow, Antonio Dimaano, Heap Hoe Kuan
-
Publication number: 20070200205Abstract: An integrated circuit package system including a leadframe with an aperture formed therein. An integrated circuit package is mounted on the leadframe over or under the aperture and a die is mounted within the aperture to the integrated circuit package.Type: ApplicationFiled: February 25, 2006Publication date: August 30, 2007Applicant: STATS CHIPPAC LTD.Inventors: Dario Filoteo, Tsz Yin Ho
-
Publication number: 20070096282Abstract: An integrated circuit package system including a high-density small footprint system-in-package with a substrate is provided. Passive components are mounted on the substrate. Solder separators are provided on the substrate, the solder separators having flattened tops at a predetermined height above the substrate. A die is supported on the solder separators above the substrate.Type: ApplicationFiled: October 29, 2005Publication date: May 3, 2007Applicant: STATS CHIPPAC LTD.Inventors: IL Kwon Shim, Tsz Yin Ho, Dario S. Filoteo, Seng Guan Chow
-
Publication number: 20060043560Abstract: A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink.Type: ApplicationFiled: July 12, 2005Publication date: March 2, 2006Applicant: STATS CHIPPAC LTD.Inventors: IL Kwon SHIM, Dario FILOTEO, Tsz Yin HO, Sebastian SOON
-
Patent number: 6943057Abstract: A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink.Type: GrantFiled: August 31, 2004Date of Patent: September 13, 2005Assignee: Stats Chippac Ltd.Inventors: IL Kwon Shim, Dario S. Filoteo, Jr., Tsz Yin Ho, Sebastian T. M. Soon