Abstract: An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.

Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In another embodiment, the probe region (14) extends over a passivation layer (18). In an application requiring very fine pitch between bond pads, the probe regions (14) and wire bond regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.

Abstract: A die (10) for an integrated circuit comprising an active area (22) is provided. The die (10) may further comprise a first ring (12) in a peripheral region of the die (10) at least partially surrounding the active area (22), wherein the first ring (12) may comprise a plurality of polygon shaped cells (32, 36). The die (10) may further comprise a second ring (14) surrounding the first ring (12), wherein the second ring (14) may comprise a plurality of polygon shaped cells (32, 36).

Abstract: An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.

Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.

Abstract: An inductive device (105) is formed above a substrate (225) having a conductive coil formed around a core (109). The coil comprises segments formed from a first plurality of bond wires (113) and a second plurality of bond wires (111). The first plurality of bond wires (113) extends between the core (109) and the substrate (225). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (117, 116). The second plurality of bond wires (111) extends over the core (109) and is coupled between two of the plurality of wire bond pads (117, 119). A shield (141) includes a portion that is positioned between the core (109) and the substrate (225).

Abstract: A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.

Abstract: A bond pad (200) has a first wire bond region (202) and a second wire bond region (204). In one embodiment, the first wire bond region (202) extends over a passivation layer (18). In an alternate embodiment, a bond pad (300) has a probe region (302), a first wire bond region (304), and a second wire bond region (306). In one embodiment, the probe region (302) and the wire bond region (304) extend over a passivation layer (18). The bond pads may have any number of wire bond and probe regions and in any configuration. The ability for the bond pads to have multiple wire bond regions allows for multiple wire connections to a single bond pad, such as in multi-chip packages. The ability for the bond pads to extend over the passivation layer also allows for reduced integrated circuit die area.

Abstract: An inductive device (105) is formed above a substrate (225) having a conductive coil formed around a core (109). The coil comprises segments formed from a first plurality of bond wires (113) and a second plurality of bond wires (111). The first plurality of bond wires (113) extends between the core (109) and the substrate (225). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (117, 116). The second plurality of bond wires (111) extends over the core (109) and is coupled between two of the plurality of wire bond pads (117, 119). A shield (141) includes a portion that is positioned between the core (109) and the substrate (225).

Abstract: A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.

Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In an application requiring very fine pitch between bond pads, the probe regions (14) and active regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.

Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.

Abstract: A bond pad (200) has a first wire bond region (202) and a second wire bond region (204). In one embodiment, the first wire bond region (202) extends over a passivation layer (18). In an alternate embodiment, a bond pad (300) has a probe region (302), a first wire bond region (304), and a second wire bond region (306). In one embodiment, the probe region (302) and the wire bond region (304) extend over a passivation layer (18). The bond pads may have any number of wire bond and probe regions and in any configuration. The ability for the bond pads to have multiple wire bond regions allows for multiple wire connections to a single bond pad, such as in multi-chip packages. The ability for the bond pads to extend over the passivation layer also allows for reduced integrated circuit die area.

Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In an application requiring very fine pitch between bond pads, the probe regions (14) and active regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.