Abstract: A delay calibration circuit includes a first delay chain, a second delay chain, and a calibration circuit. The first delay chain includes a plurality of first delay units and delays a clock signal with a first delay to generate a first delay signal. The supply current for each of the first delay units is a first current. The second delay chain includes a plurality of second delay units and a third delay unit. The second delay units delay a first signal with a second delay to generate a second delay signal. The third delay unit delays the second delay signal to generate the third delay signal. The supply current for each unit in the second delay chain is a second current. The calibration circuit adjusts a current ratio of the second current to the first current based on the second delay signal and the third delay signal.

Abstract: A calibration device, method and electronic device using the same provided by embodiments of the present disclosure only need to measure frequency values of two temperatures, then calculate frequency drift rates of various configuration combinations, and select the configuration combination with the smallest frequency drift rate to set configuration values of a trimming module. Thus, the test time can be reduced. In one embodiment, a simple heating device can be directly disposed on the chip package structure of the electronic device, so it is not necessary to use an external heating device for heating, and the environmental space required for placing the external heating device can be reduced.

Abstract: A successive approximation register analog-to-digital converter including a first capacitor group, a second capacitor group and a control circuit is provided. Each of the first and second capacitor groups includes a plurality of capacitors coupled to a common node. In a sampling mode, the control circuit provides an analog signal to the first capacitor group and provides a first voltage to the common node and the second capacitor group. In a sampling mode, the control circuit stops providing the first voltage to the common node and provides a second voltage to the second capacitor group. In a data converting mode, the control circuit reads voltage values of the capacitors of the first capacitor group in sequence. Each when the voltage of at least one specific capacitor in the first capacitor group is read, one capacitor of the second capacitor group is electrically floated.

Abstract: A successive-approximation-register (SAR) analog-to-digital converter (ADC) includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.

Abstract: A successive approximation register analog-to-digital converter including a first capacitor group, a second capacitor group and a control circuit is provided. Each of the first and second capacitor groups includes a plurality of capacitors coupled to a common node. In a sampling mode, the control circuit provides an analog signal to the first capacitor group and provides a first voltage to the common node and the second capacitor group. In a sampling mode, the control circuit stops providing the first voltage to the common node and provides a second voltage to the second capacitor group. In a data converting mode, the control circuit reads voltage values of the capacitors of the first capacitor group in sequence. Each when the voltage of at least one specific capacitor in the first capacitor group is read, one capacitor of the second capacitor group is electrically floated.

Abstract: A successive-approximation-register (SAR) analog-to-digital converter (ADC) is provided in the invention. The SAR ADC includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.

Abstract: A digital background calibration circuit including a digital random number generator, an analog-to-digital converter (ADC) and a plurality of switches is provided. The digital random number generator is configured to generate a first digital sequence having a plurality of bits. The ADC includes a plurality of sampling capacitors. The switches receive the first digital sequence and are coupled to the sampling capacitors. During a calibration period, the digital random number generator controls the sampling capacitors via the switches to sample the first digital sequence.

Abstract: A voltage holding circuit and an electronic device using thereof are provided. The voltage holding circuit includes a first transistor, a second transistor, and a first capacitor. A first terminal of the first transistor is coupled to an input voltage, and a control terminal of the first transistor receives a control signal. A first terminal of the second transistor is coupled to a second terminal of the first transistor, a second terminal of the second transistor is an output terminal of the voltage holding circuit, and a control terminal of the second transistor receives the control signal. A first terminal of the first capacitor is coupled to the second terminal of the first transistor and the first terminal of the second transistor. A holding voltage on the first terminal of the first capacitor is maintained by the first capacitor and parasitic diodes of the first transistor and the second transistor.

Abstract: A digital background calibration circuit including a digital random number generator, an analog-to-digital converter (ADC) and a plurality of switches is provided. The digital random number generator is configured to generate a first digital sequence having a plurality of bits. The ADC includes a plurality of sampling capacitors. The switches receive the first digital sequence and are coupled to the sampling capacitors. During a calibration period, the digital random number generator controls the sampling capacitors via the switches to sample the first digital sequence.

Abstract: A voltage holding circuit and an electronic device using thereof are provided. The voltage holding circuit includes a first transistor, a second transistor, and a first capacitor. A first terminal of the first transistor is coupled to an input voltage, and a control terminal of the first transistor receives a control signal. A first terminal of the second transistor is coupled to a second terminal of the first transistor, a second terminal of the second transistor is an output terminal of the voltage holding circuit, and a control terminal of the second transistor receives the control signal. A first terminal of the first capacitor is coupled to the second terminal of the first transistor and the first terminal of the second transistor. A holding voltage on the first terminal of the first capacitor is maintained by the first capacitor and parasitic diodes of the first transistor and the second transistor.