Abstract: An apparatus including: a transmitter output impedance matching circuit including an inductive element; a low noise amplifier (LNA) including a first field effect transistor (PET); a receiver input impedance matching circuit, including: a transformer including a first winding and a second winding; and a capacitor coupled in series with the first winding between a first end of the inductive element and a gate of the first FET, wherein the second winding is coupled to a second end of the inductive element; and a radio frequency (RF) port coupled between the first end of the inductive element and the capacitor.

Abstract: An apparatus, including: an oscillator configured to generate a clock signal; a clock signal synthesizer configured to generate a first clock signal, a second clock signal, and a third clock signal, wherein the first, second, and third clock signals are based on the clock signal; a baseband transmitter configured to generate a transmit baseband digital signal in response to the first clock signal; an ultra-wideband (UWB) pulse digital-to-analog converter (DAC) configured to generate a UWB pulse signal based on the transmit baseband digital signal in response to the second clock signal; and a frequency upconverter configured to frequency upconvert the UWB pulse signal to generate a transmit radio frequency (RF) signal based on the third clock signal.

Abstract: An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.

Abstract: An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.