Patents by Inventor Tu To Dang
Tu To Dang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12189532Abstract: A system includes at least one memory controller that partitions at least one memory into a plurality of nodes. Blast zones are formed that each include a predetermined number of nodes. Cache lines are erasure encoded to be stored in one or more blast zones with at least two nodes in a blast zone storing respective portions of a cache line and at least one node in the blast zone storing a parity portion. In one aspect, it is determined that data stored in one or more nodes of a blast zone needs to be reconstructed and stored in one or more spare nodes designated to replace the one or more nodes. Erasure decoding is performed using data from one or more other nodes in the blast zone to reconstruct the data for storage in the one or more spare nodes.Type: GrantFiled: June 29, 2022Date of Patent: January 7, 2025Assignee: Western Digital Technologies, Inc.Inventors: Dejan Vucinic, Jaco Hofmann, Paul Loewenstein, Huynh Tu Dang, Marjan Radi
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Publication number: 20240330656Abstract: A generator is configured to generate a domain-independent representation of an input data sample, an encoder is configured to generate a domain-dependent representation of the input data sample, and a decoder is configured to ensure that a combination of the domain-independent representation and the domain-dependent representation contains sufficient information to reconstruct the input data sample. A discriminator is configured to attempt to determine an originating domain of the domain-independent representation and a classifier is configured to classify the input data sample based on the domain-independent representation of the input data sample.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Inventors: Mark Wegman, Yuhai Tu, Xuan-Hong Dang, Ankush Singla, Adrian Shuai Li
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Publication number: 20240004795Abstract: A system includes at least one memory controller that partitions at least one memory into a plurality of nodes. Blast zones are formed that each include a predetermined number of nodes. Cache lines are erasure encoded to be stored in one or more blast zones with at least two nodes in a blast zone storing respective portions of a cache line and at least one node in the blast zone storing a parity portion. In one aspect, it is determined that data stored in one or more nodes of a blast zone needs to be reconstructed and stored in one or more spare nodes designated to replace the one or more nodes. Erasure decoding is performed using data from one or more other nodes in the blast zone to reconstruct the data for storage in the one or more spare nodes.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Dejan Vucinic, Jaco Hofmann, Paul Loewenstein, Huynh Tu Dang, Marjan Radi
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Patent number: 11297010Abstract: A programmable network switch includes at least one pipeline including a packet parser configured to parse packets received by the programmable network switch. The programmable network switch further includes a plurality of ports for communication with a plurality of Data Storage Devices (DSDs). Packets comprising commands are received by the programmable network switch to perform at least one of retrieving data from and storing data in the plurality of DSDs. The commands are sent by the programmable network switch to the plurality of DSDs via the plurality of ports, and the use of each port for sending the commands is monitored. According to one aspect, it is determined which port to use to send a command based on the monitored use of at least one port of the plurality of ports.Type: GrantFiled: December 23, 2019Date of Patent: April 5, 2022Assignee: Western Digital Technologies, Inc.Inventors: Chao Sun, Pietro Bressana, Dejan Vucinic, Huynh Tu Dang
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Publication number: 20210194830Abstract: A programmable network switch includes at least one pipeline including a packet parser configured to parse packets received by the programmable network switch. The programmable network switch further includes a plurality of ports for communication with a plurality of Data Storage Devices (DSDs). Packets comprising commands are received by the programmable network switch to perform at least one of retrieving data from and storing data in the plurality of DSDs. The commands are sent by the programmable network switch to the plurality of DSDs via the plurality of ports, and the use of each port for sending the commands is monitored. According to one aspect, it is determined which port to use to send a command based on the monitored use of at least one port of the plurality of ports.Type: ApplicationFiled: December 23, 2019Publication date: June 24, 2021Inventors: Chao Sun, Pietro Bressana, Dejan Vucinic, Huynh Tu Dang
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Patent number: 9081758Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.Type: GrantFiled: August 18, 2014Date of Patent: July 14, 2015Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Tu To Dang, Juan Q. Hernandez, Sumeet Kochar, Jung H. Yoon
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Patent number: 8990479Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.Type: GrantFiled: July 30, 2012Date of Patent: March 24, 2015Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Tu To Dang, Juan Q. Hernandez, Sumeet Kochar, Jung H. Yoon
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Publication number: 20150006967Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.Type: ApplicationFiled: August 18, 2014Publication date: January 1, 2015Inventors: Tu To Dang, John Q. Hernandez, Sumeet Kochar, Jung H. Yoon
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Publication number: 20140032819Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tu To Dang, Juan Q. Hernandez, Sumeet Kochar, Jung H. Yoon
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Publication number: 20120239981Abstract: Error reporting software-based method where an error list for a currently-running version of some target software (or firmware) is compared to an error list for a previous versions. Helpful information can be gleaned from the comparison of error lists. For example, if it is known that the hardware configuration has not changed, as between the two lists, and there is an error on the current list that does not appear on the previous list, then this indicates that the error is in the software update and is not a hardware problem.Type: ApplicationFiled: March 15, 2011Publication date: September 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey Michael Franke, Tu To Dang, Michael C. Elles, James A. Vignola
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Patent number: 7187652Abstract: A routing system and method are provided which use a composite cost in identifying routes. This allows a simple way of identifying the best route taking multiple metrics into account for each link simultaneously. The system allows for the inclusion of pruning constraints, and allows for various objectives such as bin packing or load balancing to be achieved.Type: GrantFiled: May 23, 2002Date of Patent: March 6, 2007Assignee: Tropic Networks Inc.Inventors: Byoung-Joon Lee, Sudhakar Ganti, Anand Srinivasan, Walter Joseph Carpini, Udo Mircea Neustadter, Cuong Tu Dang, Vincent Chi Chiu Wong
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Patent number: 6968131Abstract: In an optical WDM network, each optical channel is modulated with a respective channel identity. Detectors, conveniently at multiplex ports of optical band filters, detect the channel identities of all of the optical channels in an optical signal at the respective points to produce respective channel lists. A network management system determines channel lists for through ports of the optical band filters, identifies matching pairs of channel lists to determine a topology of each node and to identify optical paths entering or leaving each node, and identifies matching pairs of channel lists for these paths to determine an inter-node topology of the network. The channel identity detector points can alternatively be at the optical paths entering or leaving each node.Type: GrantFiled: September 27, 2001Date of Patent: November 22, 2005Assignee: Tropic Networks Inc.Inventors: Paul David Obeda, Robert Michael Bierman, Cuong Tu Dang, David Edward Nelles, Udo Mircea Neustadter
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Patent number: 6925061Abstract: A routing system and method are provided which use a composite cost in identifying routes. This allows a simple way of identifying the best route taking multiple metrics into account for each link simultaneously. The system allows for the inclusion of pruning constraints, and allows for various objectives such as bin packing or load balancing to be achieved.Type: GrantFiled: December 26, 2001Date of Patent: August 2, 2005Assignee: Tropic Network Inc.Inventors: Byoung-Joon Lee, Sudhakar Ganti, Anand Srinivasan, Walter Joseph Carpini, Udo Mircea Neustadter, Cuong Tu Dang, Vincent Chi Chiu Wong
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Patent number: 6882627Abstract: Methods, systems, computer readable media are provided which facilitate the selection of multiple paths through a network represented by a network topology which take into account shared risk which may exist between network resources. The method involves identifying a first path through the network topology from a source node to a destination node, the first path comprising a first sequence of network resources. For at least one shared risk group, a determination is made if any of the at least one shared risk group includes any of the first sequence of network resources, a shared risk group being a group of network resources within the network topology which have a shared risk. A topology transformation is performed of the network topology into a virtual topology which discourages the use of network resources in any shared risk group determined. A second path through the virtual topology is identified from the source node to the destination.Type: GrantFiled: June 14, 2001Date of Patent: April 19, 2005Assignee: Tropic NetworksInventors: Peter Steven Pieda, Walter Joseph Carpini, Cuong Tu Dang, Kelvin Ross Edmison, Udo Mircea Neustadter
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Publication number: 20040125745Abstract: Methods and systems for re-routing a connection through an explicitly routed network. The methods involve initially re-routing the connection to a reduced constraint connection through the network; establishing a fully constrained path through the network; subsequently re-routing the connection to the fully constrained connection through the network.Type: ApplicationFiled: April 9, 2002Publication date: July 1, 2004Applicant: AR CardInventors: Cuong Tu Dang, Udo Mircea Neustadter, Walter Joseph Carpini, John William Spicer
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Publication number: 20030189896Abstract: Methods and systems for re-routing a connection through an explicitly routed network. The methods involve initially re-routing the connection to a reduced constraint connection through the network; establishing a fully constrained path through the network; subsequently re-routing the connection to the fully constrained connection through the network.Type: ApplicationFiled: April 9, 2002Publication date: October 9, 2003Applicant: AR CardInventors: Cuong Tu Dang, Udo Mircea Neustadter, Walter Joseph Carpini, John William Spicer
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Publication number: 20030118027Abstract: A routing system and method are provided which use a composite cost in identifying routes. This allows a simple way of identifying the best route taking multiple metrics into account for each link simultaneously. The system allows for the inclusion of pruning constraints, and allows for various objectives such as bin packing or load balancing to be achieved.Type: ApplicationFiled: December 26, 2001Publication date: June 26, 2003Inventors: Byoung-Joon Lee, Sudhakar Ganti, Anand Srinivasan, Walter Joseph Carpini, Udo Mircea Neustadter, Cuong Tu Dang, Vincent Chi Chiu Wong
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Publication number: 20030118024Abstract: A routing system and method are provided which use a composite cost in identifying routes. This allows a simple way of identifying the best route taking multiple metrics into account for each link simultaneously. The system allows for the inclusion of pruning constraints, and allows for various objectives such as bin packing or load balancing to be achieved.Type: ApplicationFiled: May 23, 2002Publication date: June 26, 2003Inventors: Byoung-Joon Lee, Sudhakar Ganti, Anand Srinivasan, Walter Joseph Carpini, Udo Mircea Neustadter, Cuong Tu Dang, Vincent Chi Chiu Wong
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Patent number: 6552889Abstract: A power FET and a replica FET on a semiconductor chip coupled to a logic control circuit on a second semiconductor chip within a single housing. A power FET and a scaled down replica of the power FET are disposed on a semiconductor chip. The power FET is used as a switch to couple a DC power source to a load. A fraction of the power FET drain current passes through the replica FET and an external resistance. When the voltage across the external resistance exceeds a maximum value based upon the maximum allowable power FET drain current, the logic control circuit enters into a pulsed gate (PG) mode of operation. The first step in the PG mode is to switch both FETs into a non-conducting state for a predefined period of time. After this time period, a ramp voltage applied between gate and source of both FETs will switch them back into a current conducting state while holding the power FET drain current below its upper limit in the presence of a high capacitance load.Type: GrantFiled: July 17, 2001Date of Patent: April 22, 2003Assignee: Vishay SiliconixInventors: John Huang, Hamza Yilmaz, Mohamed N. Darwish, Wharton McDaniel, Kyle Terrill, Peter Tu Dang
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Publication number: 20030058496Abstract: In an optical WDM network, each optical channel is modulated with a respective channel identity. Detectors, conveniently at multiplex ports of optical band filters, detect the channel identities of all of the optical channels in an optical signal at the respective points to produce respective channel lists. A network management system determines channel lists for through ports of the optical band filters, identifies matching pairs of channel lists to determine a topology of each node and to identify optical paths entering or leaving each node, and identifies matching pairs of channel lists for these paths to determine an inter-node topology of the network. The channel identity detector points can alternatively be at the optical paths entering or leaving each node.Type: ApplicationFiled: September 27, 2001Publication date: March 27, 2003Inventors: Paul David Obeda, Robert Michael Bierman, Cuong Tu Dang, David Edward Nelles, Udo Mircea Neustadier