Abstract: According to an embodiment of the invention, a processor comprises a register file and a register stack engine. The register file has a predetermined size and a set of registers in the register file is allocated when a function in a code sequence is called. The register stack engine saves the contents of a set of registers in a reserve storage area responsive to a function call if the function call would overflow the predetermined size of the register file. The register stack engine restores data from the reserve storage area to the register file if a recursive function call occurs.

Abstract: A processor for executing a code sequence that includes multiple function calls comprising a register file having a predetermined size and a means for allocating sets of registers on a per-function call basis. A reserve storage area is included and a means for saving a particular set of registers in the reserve storage area responsive to a function call that would overflow the predetermined size of the register file.

Abstract: A microprocessor includes a cache memory, a bus interface unit, and an execution engine. The bus interface unit is connected to the cache memory and adapted to receive compressed data from a main memory. The execution engine is connected to the bus interface unit and adapted to receive the compressed data from the bus interface unit. The execution engine decompresses the compressed data into uncompressed data and transmits the uncompressed data to the bus interface unit. The bus interface unit is further adapted to transmit the uncompressed data to the cache memory. The microprocessor may be used in a microprocessor system having a main memory capable of storing compressed data, where the bus interface unit transfers compressed data from the main memory to the cache memory in the microprocessor. A method is also provided for increasing memory bandwidth in a microprocessor system including a microprocessor having a cache memory.

Abstract: A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result.

Abstract: A method of multiplying and accumulating two sets of values in a computer system. A packed multiply add is performed on a first portion of a first set of values packed into a first source and a first portion of a second set of values packed into a second source to generate a first result. The first result is unpacked into a plurality of values (e.g. two). The plurality of values is then added together to form a resulting accumulation value.

Abstract: A transform coefficient matrix is factorized in two submatrices of coefficients. One submatrix is applied to a subword formed of selected input data points and the other submatrix is applied to a subword formed of other selected input data points. This provides two sets of transformed output words. These transformed output data words are then combined. The two subwords may include, respectively, the odd data points and the even data points of the input data word. Alternately, the two subwords may include the high order data points and the low order data points. The transform performed by these operations may be the forward discrete cosine transform or the inverse discrete cosine transform. The submatrices of coefficients may be applied to differences of data points as well as to sums of data points. The differences and sums of data points may be applied to the submatrices of transform coefficients by the use of respective circular buffers.

Abstract: A hybrid 2-D digital convolver in a video image processor to enhance or supress image characteristics comprises a rectangular array of delay elements of pixel duration arranged in rows and columns. A digital serial stream of data encoding pixel values of a 2-D image is coupled to successive rows of delay elements of the array in horizontal-line lengths. The pixel values are modified in a multiplier of preselected weight in series with the input of each columnar delay element in a row. An adder connected between pixel delay elements in each row combines weighted inputs and outputs from prior delay elements. The output of the last delay element of each row is combined with the row outputs of prior rows and the output of the adder following the output of the last delay element off the last row forms the processed output of the convolver. The arrangement of adders and delay elements in each row avoids cumulative adder delays and thereby improves image processing efficiency.

Abstract: An adaptive digital filter can be implemented on a single Very Large Scale Integrated (VLSI) circuit silicon chip and the Least Mean Square adaptive filter algorithm can be performed by parallel processing during a single clock cycle. The adaptive filter contains dual delay lines to yield a sequence of simultaneous samples of both input and output signals. Correlations of the present error difference with previous samples of both input and output signals can then take place simultaneously in each clock cycle. The adaptive filter is modular and can be cascaded with other identical filters to form a high-order filter.

Abstract: A binary adder stage in which the two binary inputs are logically combined to produce the Exclusive-OR, the Exclusive-NOR, the NAND and the NOR functions of the two inputs. The carry-input signal is then used to control the generation of the sum output and the carry-output. When the carry-input signal has one binary value, the Exclusive-OR function and the AND function of the binary inputs are produced at the SUM and C.sub.OUT outputs. When the carry-input signal has the other binary value the Exclusive-NOR function and the OR function of the two binary inputs are produced at the SUM and C.sub.OUT outputs.