Abstract: A computer implemented method performs data skipping in a hierarchically organized computing system. A group of processor units determines leaf node data sketches for data in leaf nodes in the hierarchically organized computing system. The leaf node data sketches summarize attributes of data in the leaf nodes. The group of processor units aggregates the leaf node data sketches at intermediate nodes in the hierarchically organized computing system to form aggregated data sketches at the intermediate nodes and retains data sketches received at the intermediate nodes from a group of child nodes to form retained data sketches. The retained data sketches are one of leaf node data sketches and the aggregated data sketches. The group of processor units searches the data using the retained data sketches and the data skipping within the hierarchically organized computing system in response to queries made to the intermediate nodes in the hierarchically organized computing system.

Abstract: A computer implemented method performs data skipping in a hierarchically organized computing system. A group of processor units determines leaf node data sketches for data in leaf nodes in the hierarchically organized computing system. The leaf node data sketches summarize attributes of data in the leaf nodes. The group of processor units aggregates the leaf node data sketches at intermediate nodes in the hierarchically organized computing system to form aggregated data sketches at the intermediate nodes and retains data sketches received at the intermediate nodes from a group of child nodes to form retained data sketches. The retained data sketches are one of leaf node data sketches and the aggregated data sketches. The group of processor units searches the data using the retained data sketches and the data skipping within the hierarchically organized computing system in response to queries made to the intermediate nodes in the hierarchically organized computing system.

Abstract: A mechanism is provided in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions that are executed by the at least one processor and configure the at least one processor to implement a medical record to illustrative medical image translation engine. The medical record to illustrative medical image translation engine receives a medical record batch from storage for a patient and generates one or more predicted prognosis records based on the medical record batch using a neural network. The medical record to illustrative medical image translation engine converts the one or more predicted prognosis records to illustrative medical images using a first agent. The medical record to illustrative medical image translation engine generates a presentation of disease progression using the illustrative medical images and outputs the presentation to a user.

Abstract: A mechanism is provided in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions that are executed by the at least one processor and configure the at least one processor to implement a medical record to illustrative medical image translation engine. The medical record to illustrative medical image translation engine receives a medical record batch from storage for a patient and generates one or more predicted prognosis records based on the medical record batch using a neural network. The medical record to illustrative medical image translation engine converts the one or more predicted prognosis records to illustrative medical images using a first agent. The medical record to illustrative medical image translation engine generates a presentation of disease progression using the illustrative medical images and outputs the presentation to a user.

Abstract: A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

Abstract: A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

Abstract: A system and method for detecting speed related defects in an electronic assembly includes application specific integrated circuits (ASICs) designed with registered I/O's to provide true at-speed testing of the electronic assembly. An interconnect test engine and a test access port controller control the generation of a progressive binary patterns. The test engine receives captured data from the other ASICs in response to the binary patterns. The method includes generating binary progressive scan patterns for the output registers of one ASIC that are scanned and captured at the input registers of another ASIC. The test results are stored in a multiple input shift register (MISR) where they can be accessed for examination and diagnostic evaluations.

Abstract: A boundary scan cell including a three-state output buffer, a test data scan flip-flop for providing an input to the three-state buffer, a control data scan flip-flop for receiving a serial control data input, independent clock signals for independently clocking the test data scan flip-flop and the control data scan flip-flop, and control circuitry for controllably providing the output of the control data scan flip-flop to the three-state output driver such that the enabled state of the three-state output buffer is controlled by the output of the control data scan flip-flop, whereby the enabled state of the three-state output driver is controlled independently of the test data in the test data scan flip-flop.

Abstract: Boundary scan cells including mask circuitry having a mask latch for storing a mask flag that is serially scanned into the cell via a scan flip-flop. In a boundary scan cell having an output function, control circuitry responsive to the mask flag forces or holds the output of the cell at a state determined by one or more values scanned into the cell via the scan flip-flop if the mask flag is of a predetermined state that indicates the cell is masked. In a boundary scan cell having an input function, control circuitry responsive to the mask flag connects the output of the scan flip-flop to the input of the scan flip-flop if the mask flag is of a predetermined state that indicates the cell is masked.