Abstract: An embodiment of the invention is directed to a method for accessing configuration registers. An indication that an attempt has been made to access a first register is received. This first register reflects an index variable that points to a configuration register. Next, an indication that an attempt has been made to access a second register is received. This second register reflects part of the contents of a configuration register to which the index variable points. Next, without waiting for another attempt to access the first register, the index variable is changed to point to another configuration register. Other embodiments are also described and claimed.

Abstract: Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.

Abstract: An interrupt controller includes circuitry to process at least one end of interrupt (EOI) vector, the circuitry being capable of substantially simultaneously comparing the at least one EOI vector with a plurality of interrupts.

Abstract: A circuit and flowchart for preventing a live lock situation.

Abstract: An interrupt controller includes circuitry to process at least one end of interrupt (EOI) vector, the circuitry being capable of substantially simultaneously comparing the at least one EOI vector with a plurality of interrupts

Abstract: A system includes a scalability port switch (SPS) and a plurality of nodes. The SPS has a plurality of ports, each port coupled to a node. Each port is connected to a scalability port protocol distributed (SPPD). A snoop filter in the SPS tracks which nodes may be using various memory addresses. A scalability port protocol central (SPPC) is responsible for processing messages to support coherent and non-coherent transactions in the system.

Abstract: In a multi-node computing system, the originating receiving device receives a broadcast request, decodes the broadcast request, and transmits a broadcast header to a primary tagging device. The primary tagging device generates at least one tagged broadcast header and transmits the at least one tagged broadcast header to the originating receiving device. The originating receiving device transmits tagged broadcast transaction(s) to broadcast receiving device(s). The broadcast receiving device(s) transmits the tagged broadcast transaction(s) to a broadcast node(s). The broadcast node(s) transmits a node completion signal(s) to the broadcast receiving device(s). The broadcast receiving device(s) transmits all of the node completion signal(s) to the primary tagging device. The primary tagging device transmits a transaction completion signal to the originating receiving device.

Abstract: An interrupt vector is issued by an interrupt controller in response to an interrupt request. A processor executes an interrupt service routine in response to receiving the interrupt vector. Upon the completion of the interrupt service routine, the processor issues an end of interrupt vector to the interrupt controller. The interrupt controller substantially simultaneously compares the end of interrupt vector with a plurality of stored interrupt vectors.

Abstract: Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.

Abstract: A mapping unit is described for use in a computer system having a multiple bank memory. Each bank of the multiple bank memory includes a plug-in socket defining first and second memory rows. The mapping unit maps a memory control signal for the second row of a first socket adapted to mount one of a single-sided memory element or a double-sided memory element, to the first row of a second socket adapted to mount one of a single-sided memory element or a double-sided memory element, to provide a logical double-sided memory element when single-sided memory elements are plugged into the sockets. A poll routine in the computer system operates to determine the existence of single-sided memory elements in each of the first socket and the second socket, and asserts a select signal when the determination is positive.

Abstract: A multiprocessor computer system includes specially designed snoop circuitry to prevent data loss during write-back cycles. A memory controller within a main memory module determines if a data request at a specified address corresponds to a cacheable memory address. If it is determined that the requested data is located at a cacheable memory address, then the memory controller initiates a snoop cycle. When a snoop cycle is initiated, a write-back buffer within the main memory module is first examined to determine if data contained within the write-back buffer is the requested data, so that the data within the write-back buffer has an associated address which is the designated cacheable memory address. If the write-back buffer does not contain the requested data, then the memory controller causes the cache memories associated with the multiple processors within the multiprocessor system to be examined.