Patents by Inventor Tuan P. Do
Tuan P. Do has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6859402Abstract: An apparatus may include at least a first transistor, a second transistor, and a circuit. The first transistor has a first control terminal coupled to receive a first dynamic data signal, and is coupled to a first node. The first transistor drives a first state on the first node responsive to an assertion of the first dynamic data signal. The second transistor is coupled to the first node and has a second control terminal. The second transistor is drives a second state on the first node responsive to a signal on the second control terminal. The circuit is coupled to generate the signal on the second control terminal and is coupled to receive a second dynamic data signal. The second dynamic data signal is a complement of the first dynamic data signal, wherein the circuit is activates the second transistor responsive to an assertion of the second dynamic data signal.Type: GrantFiled: November 17, 2003Date of Patent: February 22, 2005Assignee: Broadcom CorporationInventors: Brian J. Campbell, Tuan P. Do
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Publication number: 20040100829Abstract: An apparatus may include at least a first transistor, a second transistor, and a circuit. The first transistor has a first control terminal coupled to receive a first dynamic data signal, and is coupled to a first node. The first transistor drives a first state on the first node responsive to an assertion of the first dynamic data signal. The second transistor is coupled to the first node and has a second control terminal. The second transistor is drives a second state on the first node responsive to a signal on the second control terminal. The circuit is coupled to generate the signal on the second control terminal and is coupled to receive a second dynamic data signal. The second dynamic data signal is a complement of the first dynamic data signal, wherein the circuit is activates the second transistor responsive to an assertion of the second dynamic data signal.Type: ApplicationFiled: November 17, 2003Publication date: May 27, 2004Inventors: Brian J. Campbell, Tuan P. Do
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Patent number: 6674671Abstract: An apparatus may include at least a first transistor, a second transistor, and a circuit. The first transistor has a first control terminal coupled to receive a first dynamic data signal, and is coupled to a first node. The first transistor drives a first state on the first node responsive to an assertion of the first dynamic data signal. The second transistor is coupled to the first node and has a second control terminal. The second transistor is drives a second state on the first node responsive to a signal on the second control terminal. The circuit is coupled to generate the signal on the second control terminal and is coupled to receive a second dynamic data signal. The second dynamic data signal is a complement of the first dynamic data signal, wherein the circuit is activates the second transistor responsive to an assertion of the second dynamic data signal.Type: GrantFiled: August 14, 2002Date of Patent: January 6, 2004Assignee: Broadcom Corp.Inventors: Brian J. Campbell, Tuan P. Do
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Patent number: 6630856Abstract: A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of differential output nodes responsive to two or more pairs of differential data inputs being active. A first subcircuit including a first N-channel transistor and a second N-channel transistor is configured to receive at least a first input signal and a second input signal and to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. Additionally, a second subcircuit including a third N-channel transistor and a fourth N-channel transistor is configured to receive at least a third input signal and a fourth input signal and to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active.Type: GrantFiled: December 6, 2002Date of Patent: October 7, 2003Assignee: Broadcom CorporationInventors: Tuan P. Do, Brian J. Campbell
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Publication number: 20030062944Abstract: A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of differential output nodes responsive to two or more pairs of differential data inputs being active. A first subcircuit including a first N-channel transistor and a second N-channel transistor is configured to receive at least a first input signal and a second input signal and to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. Additionally, a second subcircuit including a third N-channel transistor and a fourth N-channel transistor is configured to receive at least a third input signal and a fourth input signal and to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active.Type: ApplicationFiled: December 6, 2002Publication date: April 3, 2003Applicant: Broadcom CorporationInventors: Tuan P. Do, Brian J. Campbell
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Patent number: 6522189Abstract: A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of differential output nodes responsive to two or more pairs of differential data inputs being active. A first subcircuit including a first N-channel transistor and a second N-channel transistor is configured to receive at least a first input signal and a second input signal and to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. Additionally, a second subcircuit including a third N-channel transistor and a fourth N-channel transistor is configured to receive at least a third input signal and a fourth input signal and to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active.Type: GrantFiled: October 2, 2000Date of Patent: February 18, 2003Assignee: Broadcom CorporationInventors: Tuan P. Do, Brian J. Campbell
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Patent number: 5859552Abstract: A slew rate control circuit for an output circuit of an integrated circuit includes an input node for obtaining an input signal and an output node for providing an output signal. A first stage of the control circuit includes at least one transistor having a control terminal and first and second main terminals. The control terminals of each at least one transistor are connected together to the input node. The first main terminal of each at least one transistor are connected to a voltage rail. The second main terminal of each at least one transistor is connected to the output node through its own individual resistor. One or more subsequent stages of the control circuit each contain at least one transistor having a control terminal and first and second main terminals. The control terminals of each at least one transistor in each one or more subsequent stages of the control circuit are connected together to a control node driven from the control terminals of the preceding stage through at least one inverter.Type: GrantFiled: August 1, 1997Date of Patent: January 12, 1999Assignee: LSI Logic CorporationInventors: Tuan P. Do, Casimiro A. Stascausky