Abstract: A high-bandwidth data transfer apparatus that is suitable for modular and scalable processing systems is disclosed. In one embodiment, the data transfer apparatus includes a local bus between each of several processing devices and associated memory modules. The local busses are each coupled to a cross-bus through a bus bridge that consists of multiplexers to steer address and data signals from a local bus along the cross-bus to another local bus. The multiplexer structure of the bridges allows the cross-bus to be dynamically divided into segments in any suitable manner to support multiple concurrent links over the cross-bus. A controller is provided to set the multiplexers in accordance with transfer requests that it receives from the various processing devices. The transfer requests may be of various types such as: single transfer, block transfer, and/or message transfer. The controller may include a request queue for each type of transfer request.

Abstract: A modular, scalable system architecture that includes a data traffic master for providing high-bandwidth, shared memory connections to two or more processor units. The system architecture includes an array of memory modules coupled to an array of processor units by a traffic master. Each of the memory modules is connected to the traffic master by a data channel, and each data channel includes an address path and a data path. The data channels all share a common data path bit-width. On the other hand, the processor units are each coupled to the traffic master by data busses that have address and data path widths dictated by their design. Although the address path width of a given processor unit may be unable to span the address space of the shared memory, the processor unit can nonetheless access any memory location through the use of page pointers.

Abstract: A single-chip multiprocessor (2, 102) is disclosed. The multiprocessor (2, 102) includes multiple central processing units, or CPUs, (10, 110) that share a floating-point unit (5, 105). The floating-point unit (5, 105) may receive floating-point instruction codes from either or both of the multiple CPUs (10, 110) in the multiprocessor (2, 102), and includes circuitry (52) for decoding the floating-point instructions for execution by its execution circuitry (65). A dispatch unit (56) in the floating-point unit (5, 105) performs arbitration between floating-point instructions if more than one of the CPUs (10, 110) is forwarding instructions to the floating-point unit (5, 105) at the same time. Dedicated register banks, preferably in the form of stacks (60), are provided in the floating-point unit (5, 105).

Abstract: Logic circuitry (70, 80, 90) for performing fault detection in a microprocessor (5) is disclosed. The fault detection logic circuitry (70, 80, 90) may be implemented into a scheduler (50) in a floating-point unit (31). Mask register (M) bit positions (M.sub.0 through M.sub.7) store state information relative to registers (52) or other resources in the microprocessor (5) that is to be interrogated upon scheduling of an instruction. The instruction includes an encoded address communicated on register address lines (SA) that is received by the fault detection logic circuitry (70, 80, 90). Pass gates (72) are controlled by the encoded address on the register address lines (SA) to generate a fault indicator (FLT). Partitioning of the decoding of the encoded address may be utilized for optimization of the fault detection operation.

Abstract: A microprocessor (10) and system implementing the same is disclosed, in which stack-based register address calculation is performed in a single add cycle for instructions involving a PUSH operation. The microprocessor (10) includes a floating-point unit (FPU) (31) having a register stack (52.sub.ST) and a stack pointer (FSP), for executing floating-point instructions containing relative register addresses (REG) based upon the contents (TOP) of the stack pointer (FSP). The instructions may involve PUSH operations, in which an operand is added to the stack of operands in the register stack (52.sub.ST). Register addressing circuitry (125, 125') includes an adder (122; 122') for generating the sum of the contents (TOP) of the stack pointer (FSP) and the relative register address (REG) of the instruction, and an adder/decrementer (120) for generating the sum of the contents (TOP) of the stack pointer (FSP) and the relative register address (REG) of the instruction minus one, to account for the PUSH.

Abstract: A microprocessor (5) having an on-chip floating-point unit, or FPU, (31) is disclosed. Snoop logic (37) is present in the integer pipeline to detect the presence of floating-point load instructions, in which floating-point operands are retrieved from system main memory or from on-chip cache memory (6, 16.sub.d, 18) by load/store units 40. For such operations in which the floating-point operands are of single precision or double precision, immediate formatter (70) receives the retrieved operands on load/store buses (LOAD.sub.-- DATA0, LOAD.sub.-- DATA1) and reformats the operands into a higher precision format for use internally by FPU (31). Rebias circuitry (78) is provided within immediate formatter (70) to change the bias of the exponent portion of the reformatted floating-point operands.

Abstract: A microprocessor (5) having an on-chip floating point unit (31) is disclosed. According to the disclosed embodiments, the floating-point unit (31) is arranged in pipelined fashion, and permits out-of-order execution of instructions in the event that an instruction generates an exception, such as an underflow condition. Writeback queue control circuitry (70) is provided, which includes a writeback queue buffer (74) and a multiplexer (72). The multiplexer (72) is under the control of writeback queue control logic (75), and selects either the state of the writeback bus (WB) or the contents of the writeback queue buffer (74) for application to router circuitry (54), and thus writeback to a register file (39). Upon detection of an exception, the state of the writeback bus (WB) is forwarded to the execution units (56, 58, 60) for exception handling according to microcode, with a portion of the floating-point pipeline being flushed.