Patents by Inventor Tuan Yu

Tuan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379519
    Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tuan-Yu Hung, Ching-Feng Yang, Hung-Jui Kuo, Kai-Chiang Wu, Ming-Che Ho
  • Patent number: 12131986
    Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tuan-Yu Hung, Ching-Feng Yang, Hung-Jui Kuo, Kai-Chiang Wu, Ming-Che Ho
  • Patent number: 11953079
    Abstract: A knob-driven adjusting mechanism has two fastening belts, one adjusting device, two base seats and two shafts. The fastening belt goes through a long groove. The fastening belt is formed with a tooth row on the side of the long groove. The adjusting device has a shell seat and a knob, and each fastening belt respectively goes through the shell seat. The knob is configured on the shell seat in a rotary form to drive the fastening belts. Each base seat is respectively used for the two side parts configured on an object. The base seat has two protruding support parts. Each shaft is respectively configured on each base seat. The two ends of the shaft respectively goes into each support part in the axial direction. Each shaft is respectively connected to each fastening belt, so that each fastening belt can respectively rotate in relation to the base seat.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: April 9, 2024
    Inventors: Yuan-Ming Chen, Tuan-Yu Chen, Yen-Yu Chen
  • Publication number: 20230417306
    Abstract: A knob-driven adjusting mechanism has two fastening belts, one adjusting device, two base seats and two shafts. The fastening belt goes through a long groove. The fastening belt is formed with a tooth row on the side of the long groove. The adjusting device has a shell seat and a knob, and each fastening belt respectively goes through the shell seat. The knob is configured on the shell seat in a rotary form to drive the fastening belts. Each base seat is respectively used for the two side parts configured on an object. The base seat has two protruding support parts. Each shaft is respectively configured on each base seat. The two ends of the shaft respectively goes into each support part in the axial direction. Each shaft is respectively connected to each fastening belt, so that each fastening belt can respectively rotate in relation to the base seat.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Yuan-Ming CHEN, Tuan-Yu CHEN, Yen-Yu CHEN
  • Publication number: 20230260885
    Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tuan-Yu Hung, Ching-Feng Yang, Hung-Jui Kuo, Kai-Chiang Wu, Ming-Che Ho
  • Publication number: 20230223357
    Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.
    Type: Application
    Filed: May 24, 2022
    Publication date: July 13, 2023
    Inventors: Yi-Che Chiang, Chien-Hsun Chen, Tuan-Yu Hung, Hsin-Yu Pan, Wei-Kang Hsieh, Tsung-Hsien Chiang, Chao-Hsien Huang, Tzu-Sung Huang, Ming Hung Tseng, Wei-Chih Chen, Ban-Li Wu, Hao-Yi Tsai, Yu-Hsiang Hu, Chung-Shi Liu
  • Patent number: 11658105
    Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Tuan-Yu Hung, Ching-Feng Yang, Hung-Jui Kuo, Kai-Chiang Wu, Ming-Che Ho
  • Publication number: 20210305140
    Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tuan-Yu Hung, Ching-Feng Yang, Hung-Jui Kuo, Kai-Chiang Wu, Ming-Che Ho
  • Patent number: 11018083
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tuan-Yu Hung, Ching-Feng Yang, Hung-Jui Kuo, Kai-Chiang Wu, Ming-Che Ho
  • Patent number: 11004812
    Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tuan-Yu Hung, Hung-Jui Kuo, Hsin-Yu Pan, Ming-che Ho, Tzu Yun Huang, Yen-Fu Su
  • Publication number: 20210020559
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tuan-Yu Hung, Ching-Feng Yang, Hung-Jui Kuo, Kai-Chiang Wu, Ming-Che Ho
  • Patent number: 10868353
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
  • Patent number: 10865496
    Abstract: A plating apparatus includes a plating bath, a substrate holder, an anode electrode, and a fluid stirring member. The plating bath is configured to contain a plating solution. The substrate holder is configured to hold a substrate to be plated in the plating bath. The anode electrode is disposed in the plating bath. The fluid stirring member is disposed between the anode electrode and the substrate to be plated, and includes a plurality of first stirring stripes a plurality of second stirring stripes. The first stirring stripes extend along a first direction parallel to a plating surface of the substrate to be plated. The second stirring stripes extend along a second direction intersected with the plurality of first stirring stripes and parallel to the plating surface, wherein the fluid stirring member is configured to reciprocate along the first direction and the second direction.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tuan-Yu Hung, Hung-Jui Kuo, Ming-Che Ho
  • Publication number: 20200131664
    Abstract: A plating apparatus includes a plating bath, a substrate holder, an anode electrode, and a fluid stirring member. The plating bath is configured to contain a plating solution. The substrate holder is configured to hold a substrate to be plated in the plating bath. The anode electrode is disposed in the plating bath. The fluid stirring member is disposed between the anode electrode and the substrate to be plated, and includes a plurality of first stirring stripes a plurality of second stirring stripes. The first stirring stripes extend along a first direction parallel to a plating surface of the substrate to be plated. The second stirring stripes extend along a second direction intersected with the plurality of first stirring stripes and parallel to the plating surface, wherein the fluid stirring member is configured to reciprocate along the first direction and the second direction.
    Type: Application
    Filed: March 21, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tuan-Yu Hung, Hung-Jui Kuo, Ming-Che Ho
  • Publication number: 20200106156
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Application
    Filed: April 18, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
  • Publication number: 20200091097
    Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tuan-Yu Hung, Hung-Jui Kuo, Hsin-Yu Pan, Ming-che Ho, Tzu Yun Huang, Yen-Fu Su
  • Patent number: 8496289
    Abstract: A pitman-style foldable frame structure has an innovative and unique assembled design. The frame structure includes foldable panels, a central spindle, lateral frames, oblique connecting rods, a control device, and a central connecting frame. The frame structure offers improvement over the prior art in lowering the material cost and increasing structural support strength and rigidity of the pitman-style foldable frame and achieves practical advancement and better industrial utilization effect.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: July 30, 2013
    Assignee: Shin Fang Plastic Industrial Co., Ltd.
    Inventors: Yuan-Ming Chen, Tuan-Yu Chen, Yen-Yu Chen
  • Publication number: 20130088053
    Abstract: A pitman-style foldable frame structure has an innovative and unique assembled design. The frame structure includes foldable panels, a central spindle, lateral frames, oblique connecting rods, a control device, and a central connecting frame. The frame structure offers improvement over the prior art in lowering the material cost and increasing structural support strength and rigidity of the pitman-style foldable frame and achieves practical advancement and better industrial utilization effect.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 11, 2013
    Applicant: SHIN FANG PLASTIC INDUSTRIAL CO., LTD.
    Inventors: Yuan-Ming Chen, Tuan-Yu Chen, Yen-Yu Chen
  • Publication number: 20100226651
    Abstract: A three-way optical device includes a case, a sleeve connected to one of openings of the case, photoelectric elements disposed in one of the openings, and optical filters. Each photoelectric element is associated with an optical signal. Each optical filter is located in the case, corresponding to at least two photoelectric elements, and each optical filter is disposed on an optical path of optical signals associated with the at least two corresponding photoelectric elements. Each optical filter enables the optical signal associated with at least one photoelectric element to penetrate and reflects optical signals associated with the remaining corresponding photoelectric elements, in which the optical signals reflected by the optical filter and penetrating the same optical filter have different wavelengths.
    Type: Application
    Filed: December 9, 2009
    Publication date: September 9, 2010
    Applicant: APAC OPTO ELECTRONICS INC.
    Inventors: Tuan Yu Hung, Chang You Li, Wen Chih Hsieh, I Hsiu Chen, Ling Ying Chiang
  • Patent number: 7706691
    Abstract: A transmission device having optical fiber high definition digital audio-video data interface (HDMI/DVI/UDI), in which optical fiber is utilized as the physical connection for the logical channels of the transmission device, and is used to carry images, voices and auxiliary data of the logic channels. For the half-duplex transmission mode utilized by the display data channel, the reverse unit, the serial unit, and the multi-serial unit are properly arranged, thus fulfilling the DC balance requirement of optical fiber transmission, and resolving the lower tolerance rate shortcomings of the I2C bus specification of display data channel (DDC) and the customer electronics control (CEC) channel.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: April 27, 2010
    Assignee: Apac Opto Electronics Inc.
    Inventors: Chih-Chuan Lin, Tuan-Yu Hung, Chang-You Li