Abstract: A system for optimizing one of a 5G New Radio (NR) network or a 4G Long Term Evolution (LTE) network operation, includes: an artificial intelligence (AI) engine configured to: a) implement at least one of the following: i) collection of raw training data set; ii) training of an AI agent; iii) inference generation triggered by UE; iv) using at least one of network key performance indicator (KPI) report and network operator inputs; and v) network KPI collection after application of inferences; and b) at least one of infer and apply at least one of i) network-wide optimal per-gNB or per transmission/reception point (TRP) Synchronization Signal (SS) burst set, and ii) associated channel state information reference signal (CSI-RS) configurations for downlink (DL) reference signal transmissions, thereby enhancing at least one of network transmission power efficiency and spectral efficiency.

Abstract: Wireless communications systems and methods related to intra-packet rate adaptation are provided. A first wireless communication device communicates, with a second wireless communication device, an intra-packet modulation coding scheme (MCS) switching configuration. The first wireless communication device receives, from the second wireless communication device, a communication signal including a first data packet based on the intra-packet MCS switching configuration. The first data packet includes at least a first portion encoded by a first MCS and a second portion encoded by a second MCS different from the first MCS.

Abstract: Wireless communications systems and methods related to intra-packet rate adaptation are provided. A first wireless communication device communicates, with a second wireless communication device, an intra-packet modulation coding scheme (MCS) switching configuration. The first wireless communication device receives, from the second wireless communication device, a communication signal including a first data packet based on the intra-packet MCS switching configuration. The first data packet includes at least a first portion encoded by a first MCS and a second portion encoded by a second MCS different from the first MCS.

Abstract: Certain aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device may determine an odd-exponent modulation constellation order for a group of bits; determine a parity bit location for the group of bits based at least in part on the odd-exponent modulation constellation order; and map the group of bits, with a parity bit in the parity bit location, to an odd-exponent modulation constellation of the odd-exponent modulation constellation order.

Abstract: Certain aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device may identify groups of bits of a particular size; map the groups of bits, with corresponding parity bits, to an even-exponent modulation constellation to generate an odd-exponent modulation constellation, wherein at least one corresponding parity bit, of the corresponding parity bits, is added to a group of bits, of the groups of bits, for the mapping; and transmit a signal based at least in part on the odd-exponent modulation constellation. Numerous other aspects are provided.

Abstract: A method for radio frequency (RF) pulse synchronization in a super regenerative receiver (SRR), includes receiving an input signal including an asymmetric preamble, and estimating a phase difference between the input signal and a quench signal based on the asymmetric preamble. The method further includes compensating for the phase difference.

Abstract: An apparatus and method of reducing power dissipation in a register exchange implementation of a Viterbi decoder used in a digital receiver or mass-storage system without degrading the bit error rate of the decoder, by selectively inhibiting data samples in the Viterbi decoder's register memory from being shifted if the data samples have converged to a single value. FIFO memories keep track of what data samples have converged, the order of the samples, and the converged data value, thereby keeping the decoded data in the FIFO synchronized with data continuing to be shifted through the register memory.

Abstract: An apparatus and method of reducing power dissipation in a register exchange implementation of a Viterbi decoder used in a digital receiver or mass-storage system without degrading the bit error rate of the decoder, by selectively inhibiting data samples in the Viterbi decoder's register memory from being shifted if the data samples have converged to a single value. FIFO memories keep track of what data samples have converged, the order of the samples, and the converged data value, thereby keeping the decoded data in the FIFO synchronized with data continuing to be shifted through the register memory.