Patents by Inventor Tulio Paschoalin Leao

Tulio Paschoalin Leao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11379753
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, a user input corresponding to a command in an electronic design automation environment. Embodiments may further include comparing the user input with a portion of an electronic design database. Embodiments may also include providing a final command suggestion based upon, at least in part, the comparison.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 5, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tulio Paschoalin Leao, Gabriel Guedes de Azevedo Barbosa, Artur Melo Mota Costa, Alberto Manuel Arias Drake, Guilherme Seminotti Braga, Rodrigo Fonseca Rocha Soares, Rogério de Souza Moraes, Paula Selegato Mathias, Tales Bontempo Cunha
  • Patent number: 11138357
    Abstract: A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for literals in the Boolean expression and the constraints of the IC chip. The formal verification application can also be configured to output the array of CNF files to a hardware prototyping platform. The hardware prototyping platform can be configured to execute a hardware instantiated SAT solver for the Boolean expression in each CNF file in the array of CNF files.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 5, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Tulio Paschoalin Leao, Petros Daniel Fernandes de Medeiros Félix, Julia Pinheiro de Oliveira, Arthur Ribeiro Araujo, Lucas Martins Chaves, Andrei dos Santos Silva, Pablo Nunes Agra Belmonte
  • Patent number: 10783305
    Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include providing, using at least one processor, an electronic design and isolating a combinational loop associated with the electronic design. Embodiments may further include inserting a sequential element in a loop path of the combinational loop, wherein the sequential element has a clock that is at least twice as fast as a fastest system clock associated with the electronic design. Embodiments may also include generating a property that determines whether an input and an output of the sequential element is never different and determining whether the property is true using formal verification.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: September 22, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Matheus Nogueira Fonseca, Tulio Paschoalin Leao