Patents by Inventor Tuman E. Allen
Tuman E. Allen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11223014Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.Type: GrantFiled: June 20, 2019Date of Patent: January 11, 2022Assignee: Micron Technology, Inc.Inventors: Zhe Song, Tuman E. Allen, Cole S. Franklin, Dan Gealy
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Patent number: 11038107Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.Type: GrantFiled: November 28, 2018Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
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Patent number: 10573513Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.Type: GrantFiled: August 23, 2016Date of Patent: February 25, 2020Assignee: Micron Technology, Inc.Inventors: Zhe Song, Tuman E. Allen, Cole S. Franklin, F. Daniel Gealy
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Publication number: 20190312200Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.Type: ApplicationFiled: June 20, 2019Publication date: October 10, 2019Inventors: Zhe Song, Tuman E. Allen, Cole S. Franklin, F. Daniel Gealy
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Patent number: 10256406Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.Type: GrantFiled: May 16, 2016Date of Patent: April 9, 2019Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
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Publication number: 20190097133Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.Type: ApplicationFiled: November 28, 2018Publication date: March 28, 2019Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
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Publication number: 20170331036Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.Type: ApplicationFiled: May 16, 2016Publication date: November 16, 2017Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
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Publication number: 20160365514Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.Type: ApplicationFiled: August 23, 2016Publication date: December 15, 2016Inventors: Zhe Song, Tuman E. Allen, Cole S. Franklin, F. Daniel Gealy
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Patent number: 9484196Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.Type: GrantFiled: February 25, 2014Date of Patent: November 1, 2016Assignee: MICRON TECHNOLOGY, INC.Inventors: Zhe Song, Tuman E. Allen, Cole S. Franklin, Dan Gealy
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Patent number: 9362418Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.Type: GrantFiled: January 27, 2015Date of Patent: June 7, 2016Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, David H. Wells, Tuman E. Allen
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Publication number: 20150243709Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.Type: ApplicationFiled: February 25, 2014Publication date: August 27, 2015Applicant: Micron Technology, Inc.Inventors: Zhe Song, Tuman E. Allen, Cole S. Franklin, Dan Gealy
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Publication number: 20150137214Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.Type: ApplicationFiled: January 27, 2015Publication date: May 21, 2015Inventors: Sanh D. Tang, David H. Wells, Tuman E. Allen
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Patent number: 8987108Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.Type: GrantFiled: February 10, 2014Date of Patent: March 24, 2015Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, David H. Wells, Tuman E. Allen
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Publication number: 20140206175Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.Type: ApplicationFiled: February 10, 2014Publication date: July 24, 2014Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, David H. Wells, Tuman E. Allen
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Patent number: 8648414Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.Type: GrantFiled: July 1, 2011Date of Patent: February 11, 2014Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, David H. Wells, Tuman E. Allen
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Publication number: 20130001682Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Sanh D. Tang, David H. Wells, Tuman E. Allen
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Patent number: 8143167Abstract: Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth ? between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench ? depth by utilizing three dry etch steps.Type: GrantFiled: March 3, 2009Date of Patent: March 27, 2012Assignee: Micron Technology, Inc.Inventors: Xiaolong Fang, Ramakanth Alapati, Tuman E. Allen
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Publication number: 20100062580Abstract: Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth ? between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench ? depth by utilizing three dry etch steps.Type: ApplicationFiled: March 3, 2009Publication date: March 11, 2010Applicant: Micron Technology, Inc.Inventors: Xiaolong Fang, Ramakanth Alapati, Tuman E. Allen