Abstract: A bidirectional electrostatic discharge protection device includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first bipolar junction transistor. The first diode and the first bipolar junction transistor are electrically connected to a first pin. The second transient voltage suppressor chip includes a second diode and a second bipolar junction transistor. The second diode and the second bipolar junction transistor are electrically connected to a second pin. The first conductive wire is electrically connected between the first diode and the second bipolar junction transistor. The second conductive wire is electrically connected between the second diode and the first bipolar junction transistor.

Abstract: A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

Abstract: A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.

Abstract: A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

Abstract: An embedded NMOS triggered silicon controlled rectification device includes a P-type substrate, at least one rectifying zone, and at least one trigger. The rectifying zone includes a first N-type heavily doped area, an N-type well, and a first P-type heavily doped area. Alternatively, the device includes an N-type substrate, a first P-type well, at least one rectifying zone, and at least one trigger. The rectifying zone includes a second P-type well, a first N-type heavily doped area, and a first P-type heavily doped area. The trigger cooperates with the P-type substrate or the first P-type well to form at least one NMOSFET. The trigger is independent to the rectifying zone. The first P-type heavily doped area is arranged between the trigger and the first N-type heavily doped area.

Abstract: An embedded NMOS triggered silicon controlled rectification device includes a P-type substrate, at least one rectifying zone, and at least one trigger. The rectifying zone includes a first N-type heavily doped area, an N-type well, and a first P-type heavily doped area. Alternatively, the device includes an N-type substrate, a first P-type well, at least one rectifying zone, and at least one trigger. The rectifying zone includes a second P-type well, a first N-type heavily doped area, and a first P-type heavily doped area. The trigger cooperates with the P-type substrate or the first P-type well to form at least one NMOSFET. The trigger is independent to the rectifying zone. The first P-type heavily doped area is arranged between the trigger and the first N-type heavily doped area.