Abstract: Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

Abstract: Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

Abstract: Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

Abstract: A sensing amplifier using capacitive coupling and a dynamic reference voltage, where the sensing amplifier circuit includes a bit line, configured to receive charging and discharging signals; a sensing amplifier, connected to the bit line and configured to receive the bit line and a reference voltage for comparison and configured to enlarge the voltage difference between a high point and a low point; and a reference voltage generator, connected to the sensing amplifier to generate the reference voltage required for the sensing amplifier to compare. The sensing amplifier effectively enhances sensing margin of the sensing amplifier circuit; and in addition, to accelerate the access speed, the sensing amplifier can easily determine the correct stored data and further quickly solve the problems of high-speed storing the data by the storage units.

Abstract: A sensing amplifier using capacitive coupling and a dynamic reference voltage, where the sensing amplifier circuit includes a bit line, configured to receive charging and discharging signals; a sensing amplifier, connected to the bit line and configured to receive the bit line and a reference voltage for comparison and configured to enlarge the voltage difference between a high point and a low point; and a reference voltage generator, connected to the sensing amplifier to generate the reference voltage required for the sensing amplifier to compare. The sensing amplifier effectively enhances sensing margin of the sensing amplifier circuit; and in addition, to accelerate the access speed, the sensing amplifier can easily determine the correct stored data and further quickly solve the problems of high-speed storing the data by the storage units.