Abstract: Techniques for detecting a digital pseudo-random sequence (PRS) using fast locking, including repeatedly computing a first PRS seed based on an ADC output, generating a PRS sequence based on the first seed, computing a second PRS seed based on the sequence, and comparing the sequence to the ADC output (comparison results may be provided as a bool signal), until the sequence matches the ADC output. Thereafter, the technique may include re-computing the sequence based on the second seed, re-computing the second seed based on the re-computed sequence and comparing the re-computed sequence to the ADC output. The technique may further include setting a lock when a threshold number of sequences computed from the second seed match the ADC output, and reverting to computing the sequence based on the first seed if a sequence computed from the second seed does not match the ADC output and the lock is not set.

Abstract: A processing system includes a controller of a transmitting module for transmitting data to a receiving module across an interconnect compliant with a processor interconnect protocol. The controller indicates the beginning and end of a variable-length data burst using data primitives that are N symbols (bytes) in length, rather than using data primitives that are M symbols in length, as specified by the processor interconnect protocol, where N<M. The controller of the transmitting module signals the beginning of a data burst by sending a short primitive indicating either the beginning of a data burst or signaling the receiving module to reset error detection logic so that error detection information based on the data burst can be calculated. The controller automatically inserts another short primitive indicating the end of a data burst when there is no data to transmit, thus accommodating data bursts of variable lengths.

Abstract: A processing system includes a controller of a transmitting module for transmitting data to a receiving module across an interconnect compliant with a processor interconnect protocol. The controller indicates the beginning and end of a variable-length data burst using data primitives that are N symbols (bytes) in length, rather than using data primitives that are M symbols in length, as specified by the processor interconnect protocol, where N<M. The controller of the transmitting module signals the beginning of a data burst by sending a short primitive indicating either the beginning of a data burst or signaling the receiving module to reset error detection logic so that error detection information based on the data burst can be calculated. The controller automatically inserts another short primitive indicating the end of a data burst when there is no data to transmit, thus accommodating data bursts of variable lengths.