Abstract: An artificial intelligence (AI)-enabled device including a sensor unit, an AI analysis unit, and an action execution unit, for detecting and monitoring objects and their activities within an operating field, is provided. The sensor unit captures multi-modal sensor data elements including sound, image, thermal, radio wave, and other environmental data associated with the objects along with timing data in the operating field. The AI analysis unit includes one or more AI analyzers that, in communication with an AI data library, receive and locally analyze each and an aggregate of the multi-modal sensor data elements. Based on the analysis, the AI analyzers distinguish between the objects detected and identified in the operating field, distinguish non-related sensor data, determine and monitor the activities of the identified objects, and generate and validate activity data from the activities. The action execution unit executes one or more actions in real time based on the validation.

Abstract: A high-voltage metal-oxide-semiconductor transistor device includes a semiconductor substrate, a gate structure, a first drift region, a first isolation structure, a drain region, and a first sub-gate structure. The gate structure and the first sub-gate structure are disposed on the semiconductor substrate and separated from each other. The first drift region is disposed in the semiconductor substrate and disposed at one side of the gate structure. The first isolation structure and the drain region are disposed in the first drift region and separated from each other. A part of the first drift region is disposed between the drain region and the first isolation structure. The first sub-gate structure is at least partially disposed on the first drift region disposed between the drain region and the first isolation structure, and the first sub-gate structure is electrically connected to the drain region.

Abstract: A method for forming gate structures for a HV device and a MV device is provided. The method includes forming a HV oxide layer on the substrate, covering a first region predetermined for forming the HV device. Further in the method, a dielectric mask is formed on a central portion of the HV oxide layer. A thermal oxidation process is performed to form a MV oxide layer on the substrate at a second region predetermined for forming the MV device, wherein peripheral portions of the HV oxide layer not covered by the dielectric mask grow thicker. The dielectric mask is removed. A conductive layer is formed over the substrate. The conductive layer, the HV oxide layer, the MV oxide layer are patterned to form the gate structures.

Abstract: A method of forming semiconductor devices. First, a substrate is provided, and a first implant area and a second implant area are defined in a mask pattern. Subsequently, a resist layer on the substrate is patterned using the mask pattern to form a first opening exposing the first implant area and a second opening to expose the second implant area. After that, an ion implantation process including a partial shadowing ion implant is processed, wherein the second implant area is implanted by the partial shadowing ion implant to a predetermined concentration, and the first implant area is substantially not implanted by the partial shadowing ion implant.

Abstract: A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device.

Abstract: A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device.