Patents by Inventor Tun-Wen Pi

Tun-Wen Pi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250098279
    Abstract: A method includes forming a semiconductive channel structure over a substrate. A semiconductive layer is deposited over the semiconductive channel structure. The semiconductive layer and the semiconductive channel structure includes different materials. An oxidation process is performed to the semiconductive layer to form an oxidation layer over a remaining portion of the semiconductive layer. The oxidation layer is heated after the oxidation process is performed. A gate structure is formed over the oxidation layer.
    Type: Application
    Filed: November 27, 2024
    Publication date: March 20, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Minghwei HONG, Juei-Nai KWO, Tun-Wen PI, Hsien-Wen WAN, Yi-Ting CHENG, Yu-Jie HONG
  • Patent number: 12191205
    Abstract: A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Minghwei Hong, Juei-Nai Kwo, Tun-Wen Pi, Hsien-Wen Wan, Yi-Ting Cheng, Yu-Jie Hong
  • Publication number: 20230011006
    Abstract: A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.
    Type: Application
    Filed: March 3, 2022
    Publication date: January 12, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Minghwei HONG, Juei-Nai KWO, Tun-Wen PI, Hsien-Wen WAN, Yi-Ting CHENG, Yu-Jie HONG
  • Patent number: 9214518
    Abstract: Disclosed is a wafer comprising a first layer of GaSb grown on a GaSb substrate by molecular beam epitaxy (MBE), an oxide layer deposited on the surface of the first layer, and a cap layer deposited on the surface of the oxide layer. The wafer was capped with an arsenic (As) layer after the growth of the first layer. The As layer was removed from the wafer before the oxide layer was deposited on the surface of the first layer. Also disclosed is a method of forming a wafer. The method comprises growing a first layer of GaSb on a GaSb substrate by MBE, capping the wafer with an As layer after the growth of the first layer, removing the As layer from the wafer, depositing an oxide layer on the surface of the first layer, and depositing a cap layer on the surface of the oxide layer.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited and National Taiwan University
    Inventors: Jui-Lin Chu, Ming-Hwei Hong, Juei-Nai Kwo, Tun-Wen Pi, Jen-Inn Chyi
  • Patent number: 8859441
    Abstract: The present invention provides a system and method for manufacturing a semiconductor device including a substrate and a high-? dielectric layer on the substrate. The system comprises a modular track; a substrate-forming chamber connected with the modular track for forming the substrate; and an atomic layer deposition (ALD) chamber connected with the modular track for providing the high-? dielectric layer.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: October 14, 2014
    Inventors: Ming-Hwei Hong, Ray-Nien Kwo, Tun-Wen Pi, Mao-Lin Huang, Yu-Hsing Chang, Pen Chang, Chun-An Lin, Tsung-Da Lin
  • Publication number: 20130267077
    Abstract: The present invention provides a system and method for manufacturing a semiconductor device including a substrate and a high-? dielectric layer on the substrate. The system comprises a modular track; a substrate-forming chamber connected with the modular track for forming the substrate; and an atomic layer deposition (ALD) chamber connected with the modular track for providing the high-? dielectric layer.
    Type: Application
    Filed: April 5, 2012
    Publication date: October 10, 2013
    Inventors: Ming-Hwei Hong, Ray-Nien Kwo, Tun-Wen Pi, Mao-Lin Huang, Yu-Hsing Chang, Pen Chang, Chun-An Lin, Tsung-Da Lin