Abstract: Multi-phase switching converters and methods that provide fast response and low ripple on the converter inputs and outputs. The converters include multiple converter stages that are normally operated in sequence into a common load. However upon sensing that operation of one of the converter stages does not bring the converter back into regulation, multiple converter stages are operated until regulation is reestablished, after which the converter stages are operated in sequence again. In the embodiment disclosed, upon sensing that operation of one of the converter stages does not bring the converter back into regulation, all converter stages are operated until regulation is reestablished, after which the converter stages are operated in sequence again starting with the stage with the lowest inductor current.

Abstract: Programmable voltage regulators that change from a first set-point voltage to a second set-point voltage at a controlled rate. The set-point signal is a multi-bit set-point signal with the rate of change in the regulator output between set-points being predetermined or externally controllable. Various embodiments are disclosed.

Abstract: The present invention teaches a variety of startup modes for operating a boost type switching power supply. A linear charging mode couples the input voltage directly to the output voltage, thereby precharging the output capacitor of the switching power supply. The linear mode serves to reduce inrush battery current and limit the stress voltage on the power switching devices. A pseudo-buck mode, preferably entered into after the linear mode has precharged the output capacitor, operates the boost type switching power supply in a manner providing power to the output essentially as a buck type switching power supply would. This results in continuous charging of the output capacitor, thereby reducing startup time and increasing power efficiency. The pseudo-buck mode also enables step-down voltage generation with boost type circuitry. A pseudo-boost mode facilitates a smooth transition between the pseudo-buck and traditional boost modes.

Abstract: A step-down switching regulator of the present invention includes (1) a magnetic storage device having at least one primary output and one secondary output, (2) a current sensing device for detecting current through a primary winding of the magnetic storage device, (3) a first switch, (4) a second switch, (5) a first comparator for detecting whether the current through the primary winding is greater than a limit value, (6) a second comparator for detecting loss of regulation in the secondary output, and (7) a switch logic circuitry for allowing only one of the first switch or the second switch to turn on at a time. When the primary output is out of regulation, the first switch turns on to deliver power to the primary output. When the secondary output is out of regulation, one of two methods can be used to supply power to the secondary output. A first method turns on the first switch for a short time, and then the second switch turns on to deliver power to the secondary output.

Abstract: Method and apparatus for logic signal level translation to a semiconductor switch. The logic signal input is converted by a first circuit referenced to a first power supply level to a current source or sink gated on and off by the logic signal. The resulting current is coupled to the input of a second circuit referenced to a second power supply level to control complementary devices providing a switching signal for coupling to the semiconductor switch. The second circuit preferably includes circuitry for assuring that both complementary devices cannot be on at the same time.

Abstract: A step-down switching regulator of the present invention includes (1) a magnetic storage device having at least one primary output and one secondary output, (2) a current sensing device for detecting current through a primary winding of the magnetic storage device, (3) a first switch, (4) a second switch, (5) a first comparator for detecting whether the current through the primary winding is greater than a limit value, (6) a second comparator for detecting loss of regulation in the secondary output, and (7) a switch logic circuitry for allowing only one of the first switch or the second switch to turn on at a time. When the primary output is out of regulation, the first switch turns on to deliver power to the primary output. When the secondary output is out of regulation, one of two methods can be used to supply power to the secondary output. A first method turns on the first switch for a short time, and then the second switch turns on to deliver power to the secondary output.

Abstract: A method and apparatus for increasing the light load efficiency of a DC-DC converter by reducing the quiescent power of the control section. In accordance with the invention, the DC-DC conversion is first started using a first regulator circuit to power the converter controller. When the converter output reaches an adequate level, the converter controller power input is switched to the output of the converter. At the same time, the first regulator circuit is turned off, whereby the converter controller continues to operate from the converter output, which has a voltage substantially less than the power supply input voltage. Because controllers all draw about the same current, the lower input voltage to the controller lowers the power consumption thereof, improving the efficiency of the regulator, particularly when subjected to light loads. Various embodiments are disclosed.

Abstract: An improved zener diode formed in a semiconductor wafer having a primary surface, the zener diode having a PN junction buried beneath the surface. The diode includes a pair of spaced contacts on the surface, the first located on one region and the second located on another laterally spaced region of the surface, to establish a current path through the diode. A replica device is formed on the same wafer generally replicating the physical dimensions of the zener diode. The replica device has a pair of spaced surface contacts located on spaced regions of the surface with a replica current path between them having substantially the same resistance as the on-resistance of the current path of the diode, the replica current path replicating the current path except that it has no PN junction.

Abstract: An operational amplifier or comparator is provided in which internal parasitic capacitances are buffered to increase the gain bandwidth product of the amplifier.

Abstract: An improved analog to digital converter in which an approximate digital representation is provided by a parallel analog to digital converter and the conversion is completed by a successive approximation analog to digital converter.

Abstract: An improved analog to digital converter is provided in which high and low order bytes of the digital output can be sequentially generated by a single flash converter circuit. Upon the generation of the high order byte, a high byte equivalent voltage is subtracted from the analog input voltage and the residual is multiplied by a predetermined factor. The resultant product signal is converted by the same flash converter circuit to the low order byte. In addition, the low scale and full scale of the converter inputs may be programmed to have the same polarity as, or the opposite polarity of, the polarities of the reference voltages.