Abstract: An integrated circuit having a multi-layer interconnection structure comprises a logic section of series-connected MOS FETs each having a gate input connection layer made of a polysilicon layer on a semiconductor substrate of one conductivity type and source and drain semiconductor regions of the other conductivity type formed in the surface of the substrate along such a direction as to traverse the gate input connection layer, a load device connected to one end of the logic section, and interconnection structure for causing a signal, at a junction of the load device and logic the section, to be transmitted to the other end of the logic section across the gate input connection layer.