Abstract: A semiconductor light-emitting device including a light-emitting diode chip and an electrode disposed thereon is provided. The electrode at least includes a plated silver alloy (Ag1-xYx) layer, wherein the Y of the Ag1-xYx layer includes metals forming a complete solid solution with Ag at arbitrary weight percentage, and the X of the Ag1-xYx layer is in a range from about 0.02 to 0.15. The fabricating method thereof is also provided.

Abstract: A semiconductor light-emitting device including a light-emitting diode chip and an electrode disposed thereon is provided. The electrode at least includes a plated silver alloy (Ag1-xYx) layer, wherein the Y of the Ag1-xYx layer includes metals forming a complete solid solution with Ag at arbitrary weight percentage, and the X of the Ag1-xYx layer is in a range from about 0.02 to 0.15. The fabricating method thereof is also provided.

Abstract: A solder ball includes a silver ball structure and a shell structure. The shell structure wraps a surface of the silver ball structure, and a material of the shell structure at least includes tin. When the solder ball is bonded to other devices, the ball height of the solder ball remains constant to avoid collapse.

Abstract: A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au0.35Sn0.15 to about Au0.75Sn0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.

Abstract: A chip package structure including a chip, a circuit layer, a passive element material and a substrate is provided. The circuit layer is disposed on a surface of the chip, wherein the circuit layer includes a plurality of bumps and a plurality of passive element electrodes. The bumps and the passive element electrodes have the same material, and the passive element electrodes are electrically connected with part of the bumps. The passive element material is disposed between the passive element electrodes, so that the passive element electrodes and the passive element material form a passive element located on the surface of the chip. The chip is disposed on the substrate and faces the substrate by the surface, so that the chip and the passive element are electrically connected to the substrate through the bumps. A method of manufacturing the chip package structure aforementioned is also provided.

Abstract: A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn. alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling, with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au0.35Sn0.15 to about Au0.75Sn0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by reflow operation or a thermal press operation.

Abstract: A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au0.85Sn0.15 to about Au0.75Sn0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.

Abstract: A semiconductor structure includes a device, a conductive pad over the device and a Ag1-xYx alloy pillar disposed on the conductive pad, wherein the Y of the Ag1-xYx alloy comprises metals forming complete solid solution with Ag at arbitrary weight percentage, and wherein the X of the Ag1-xYx alloy is in a range of from about 0.005 to about 0.25.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a conductive pad on a semiconductor die; forming a seed layer over the conductive pad; defining a first mask layer over the seed layer; and forming a silver alloy bump body in the first mask layer. The forming a silver alloy bump body in the first mask layer includes operations of preparing a first cyanide-based bath; controlling a pH value of the first cyanide-based bath to be within a range of from about 6 to about 8; immersing the semiconductor die into the first cyanide-based bath; and applying an electroplating current density of from about 0.1 ASD to about 0.5 ASD to the semiconductor die.

Abstract: A semiconductor structure includes a device, a conductive pad on the device, and a Ag1-xYx alloy bump over the conductive pad. The Y of the Ag1-xYx bump comprises metals forming complete solid solution with Ag at arbitrary weight percentage, and the X of the Ag1-xYx alloy bump is in a range of from about 0.005 to about 0.25. A difference between one standard deviation and a mean value of a grain size distribution of the Ag1-xYx alloy bump is in a range of from about 0.2 ?m to about 0.4 ?m. An average grain size of the Ag1-xYx alloy bump on a longitudinal cross sectional plane is in a range of from about 0.5 ?m to about 1.5 ?m.