Abstract: A process for creating a storage node structure, for a DRAM capacitor structure, featuring increased storage node surface area, via use of an HSG silicon layer, on an underlying storage node shape, has been developed. The process features the use of an isotropic, buffered HF etch procedure, applied to the HSG silicon layer, to increase the space between the concave and convex features, of the HSG silicon layer. The increased space between the concave and convex features of the HSG silicon layer, allows a capacitor dielectric layer, of uniform thickness, to be formed on the isotopically etched, HSG silicon layer.

Abstract: A process for forming a DRAM capacitor structure, comprised with a HSG silicon/polysilicon crown shaped storage node structure, has been developed. The process features the use of a series of wet clean procedures, used to prepare the surface of the HSG silicon/polysilicon, crown shaped storage node structure, for the formation of an overlying capacitor dielectric layer. A first wet clean procedure is employed after the formation of the crown shaped storage node structure via a CMP procedure, featuring an ammonium hydroxide--hydrogen peroxide solution, used to remove CMP, as well as HSG silicon particles from the surface of a photoresist plug used for definition of the crown shaped storage node structure. Another wet clean procedure, first performed in a DHF solution, then followed by a sulfuric acid--hydrogen peroxide treatment, is used to prepare the HSG silicon/polysilicon, crown shaped storage node structure, for formation of the overlying capacitor dielectric layer.