Patents by Inventor Tung-Chieh Chen

Tung-Chieh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11043396
    Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Kung, Tung-Kai Chen, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11010528
    Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: May 18, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Tung-Chieh Chen, Po-Hsun Wu, Po-Hung Lin, Tsung-Yi Ho
  • Patent number: 10719653
    Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 21, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Chien-Hung Lu, Chun-Chen Chi, Tung-Chieh Chen, Kai-Chih Chi
  • Patent number: 10409943
    Abstract: A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: September 10, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Tung-Chieh Chen, Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen
  • Publication number: 20170316143
    Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 2, 2017
    Inventors: Chien-Hung Lu, Chun-Chen Chi, Tung-Chieh Chen, Kai-Chih Chi
  • Patent number: 9747406
    Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: August 29, 2017
    Assignee: Synopsys, Inc.
    Inventors: Chien-Hung Lu, Chun-Cheng Chi, Tung-Chieh Chen
  • Patent number: 9665679
    Abstract: A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ratio for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: May 30, 2017
    Assignee: Synopsys, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Publication number: 20170124245
    Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.
    Type: Application
    Filed: January 12, 2016
    Publication date: May 4, 2017
    Inventors: Tung-Chieh Chen, Po-Hsun Wu, Po-Hung Lin, Tsung-Yi Ho
  • Patent number: 9311441
    Abstract: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: April 12, 2016
    Assignee: Synopsys Taiwan Co., Ltd.
    Inventors: Jui-Hsiang Liu, Hsin-I Lin, Tung-Chieh Chen
  • Patent number: 9286433
    Abstract: A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: March 15, 2016
    Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.
    Inventors: Tung-Chieh Chen, Hung-Ming Chen, Yi-Peng Weng
  • Patent number: 9256706
    Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: February 9, 2016
    Assignee: Synopsys Taiwan Co., Ltd.
    Inventors: Tung-Chieh Chen, Po-Hsun Wu, Po-Hung Lin, Tsung-Yi Ho
  • Publication number: 20150143322
    Abstract: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 21, 2015
    Inventors: Jui-Hsiang Liu, Hsin-I Lin, Tung-Chieh Chen
  • Publication number: 20150100938
    Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 9, 2015
    Inventors: Chien-Hung Lu, Chun-Cheng CHI, Tung-Chieh CHEN
  • Publication number: 20150067626
    Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 5, 2015
    Inventors: Tung-Chieh CHEN, Po-Hsun WU, Po-Hung LIN, Tsung-Yi HO
  • Publication number: 20150067632
    Abstract: A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 5, 2015
    Inventors: Tung-Chieh CHEN, Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen
  • Publication number: 20150007123
    Abstract: A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ration for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 8875081
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 28, 2014
    Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Publication number: 20140075402
    Abstract: A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.
    Type: Application
    Filed: November 18, 2013
    Publication date: March 13, 2014
    Applicants: Synopsys, Inc., Synopsys Taiwan Co. Ltd.
    Inventors: Tung-Chieh Chen, Hung-Ming Chen, Yi-Peng Weng
  • Publication number: 20140068542
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Application
    Filed: February 26, 2013
    Publication date: March 6, 2014
    Applicants: SpringSoft USA, Inc, SpringSoft, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 8661388
    Abstract: A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: February 25, 2014
    Assignee: Mediatek Inc.
    Inventors: Tung-Chieh Chen, Ping-Hung Yu, Yao-Wen Chang, Fwu-Juh Huang, Tien-Yueh Liu