Patents by Inventor Tung-chuan Wang
Tung-chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11145565Abstract: A power chip package module and a manufacturing method thereof are provided. In the manufacturing method, a temporary carrier having an alignment pattern is provided, in which the temporary carrier includes a base and a peelable adhesive material disposed on the base. Thereafter, a circuit board having an accommodating space passing therethrough is disposed on the temporary carrier according to the alignment pattern. Furthermore, a chip is disposed in the accommodating space with an active surface thereof facing the temporary carrier according to the alignment pattern, in which the chip is fixed on the temporary carrier by the peelable adhesive material. The accommodating space is filled with a molding material to form an initial package structure. The initial package structure is separated from the temporary carrier, and then an electrically and thermally conductive layer is formed on a bottom surface of the chip and is in contact therewith.Type: GrantFiled: June 10, 2020Date of Patent: October 12, 2021Assignee: YOUNGTEK ELECTRONICS CORPORATIONInventors: Hsi-Ying Yuan, Tung-Chuan Wang, Chun-Yuan Hou, Ping-Lung Wang, Tzu-kuei Wen
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Publication number: 20210043532Abstract: A power chip package module and a manufacturing method thereof are provided. In the manufacturing method, a temporary carrier having an alignment pattern is provided, in which the temporary carrier includes a base and a peelable adhesive material disposed on the base. Thereafter, a circuit board having an accommodating space passing therethrough is disposed on the temporary carrier according to the alignment pattern. Furthermore, a chip is disposed in the accommodating space with an active surface thereof facing the temporary carrier according to the alignment pattern, in which the chip is fixed on the temporary carrier by the peelable adhesive material. The accommodating space is filled with a molding material to form an initial package structure. The initial package structure is separated from the temporary carrier, and then an electrically and thermally conductive layer is formed on a bottom surface of the chip and is in contact therewith.Type: ApplicationFiled: June 10, 2020Publication date: February 11, 2021Inventors: HSI-YING YUAN, TUNG-CHUAN WANG, CHUN-YUAN HOU, PING-LUNG WANG, Tzu-kuei Wen
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Publication number: 20180315712Abstract: Provided is an embedded substrate package structure, including, from top to bottom, a fourth dielectric layer, a second substrate, a chip with a fifth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate and a first dielectric layer; wherein the substrates are disposed respectively with wire layers and through holes, and each of dielectric layers is disposed with openings, conductive bumps or conductive pads, wire layers, through holes, and chip to collectively form electrical connection. The chip is electrically connected to the substrate in a flip-chip manner, and the back of the chip interfaces a dielectric layer. Compared to the prior art which chip bonding is in face-up mode, the packaging structure with the face-down chip of the present invention can simplify the manufacturing process by the flip-chip method.Type: ApplicationFiled: November 20, 2017Publication date: November 1, 2018Inventors: Sung-Lien He, Chun-Yuan Hou, Tung-Chuan Wang, Hsi-Ying Yuan, Feng-Yi Chang
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Patent number: 10115673Abstract: Provided is an embedded substrate package structure, including, from top to bottom, a fourth dielectric layer, a second substrate, a chip with a fifth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate and a first dielectric layer; wherein the substrates are disposed respectively with wire layers and through holes, and each of dielectric layers is disposed with openings, conductive bumps or conductive pads, wire layers, through holes, and chip to collectively form electrical connection. The chip is electrically connected to the substrate in a flip-chip manner, and the back of the chip interfaces a dielectric layer. Compared to the prior art which chip bonding is in face-up mode, the packaging structure with the face-down chip of the present invention can simplify the manufacturing process by the flip-chip method.Type: GrantFiled: November 20, 2017Date of Patent: October 30, 2018Inventors: Sung-Lien He, Chun-Yuan Hou, Tung-Chuan Wang, Hsi-Ying Yuan, Feng-Yi Chang
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Publication number: 20180166390Abstract: Provided is a planar package structure and its manufacturing method. The planar package structure totally packages a die to make the die unexposed and to protect the die from impact or scratch. Further, at least one conductive pad of the die is electronically connected to an external electronic circuit through a plurality of wiring patterns and through holes filled with conductive materials. Then, the die may be connected to the external electronic circuit and may be protected from impact or scratch.Type: ApplicationFiled: December 9, 2016Publication date: June 14, 2018Inventors: Chao-Ching Yu, Lin-Ta Chung, Hsi-Ying Yuan, Tung-Chuan Wang
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Patent number: 7655501Abstract: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.Type: GrantFiled: June 18, 2008Date of Patent: February 2, 2010Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Tung-Chuan Wang, Chao-Nan Chou, Chih-Wei Lin
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Patent number: 7525185Abstract: The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate.Type: GrantFiled: March 19, 2007Date of Patent: April 28, 2009Assignee: Advanced Chip Engineering Technology, Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin, Tung-Chuan Wang, Hsien-Wen Hsu, Chih-Ming Chen
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Patent number: 7498556Abstract: The present invention provides an image sensor module having build-in package cavity and the Method of the same. An image sensor module structure comprising a substrate with a package receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate, and a package having a die with a micro lens disposed within the package receiving cavity. A dielectric layer is formed on the package and the substrate, a re-distribution conductive layer (RDL) is formed on the dielectric layer, wherein the RDL is coupled to the die and the conductive traces and the dielectric layer has an opening to expose the micro lens. A lens holder is attached on the substrate and the lens holder has a lens attached an upper portion of the lens holder. A filter is attached between the lens and the micro lens. The structure further comprises a passive device on the upper surface of the substrate within the lens holder.Type: GrantFiled: March 15, 2007Date of Patent: March 3, 2009Assignee: Adavanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin, Jui-Hsien Chang, Tung-Chuan Wang
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Patent number: 7459729Abstract: The present invention discloses a structure of package including: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die having micro lens area disposed within the die receiving through hole; a transparent cover covers the micro lens area; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.Type: GrantFiled: December 29, 2006Date of Patent: December 2, 2008Assignee: Advanced Chip Engineering Technology, Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Tung-chuan Wang
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Publication number: 20080274579Abstract: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper layer of the substrate, wherein terminal pads are formed on the upper surface of the substrate, the same plain as the micro lens. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die. An opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for Image Sensor chip. A protection layer (film) be coated on the micro lens area with water repellent and oil repellent to away the particle contamination. A transparent cover with coated IR filter is optionally formed over the micron lens area for protection.Type: ApplicationFiled: July 9, 2008Publication date: November 6, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Tung-Chuan Wang
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Publication number: 20080261346Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die having micro lens area disposed within the die receiving through hole; a transparent cover covers the micro lens area; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.Type: ApplicationFiled: July 1, 2008Publication date: October 23, 2008Inventors: Wen-Kun Yang, Jui-Hsien Chang, Tung-chuan Wang
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Publication number: 20080248614Abstract: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.Type: ApplicationFiled: June 18, 2008Publication date: October 9, 2008Inventors: Wen-Kun Yang, Tung-Chuan Wang, Chao-Nan Chou, Chih-Wei Lin
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Publication number: 20080230884Abstract: The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate.Type: ApplicationFiled: March 19, 2007Publication date: September 25, 2008Inventors: Wen-Kun Yang, Diann-Fang Lin, Tung-Chuan Wang, Hsien-Wen Hsu, Chih-Ming Chen
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Publication number: 20080224248Abstract: The present invention provides an image sensor module having build-in package cavity and the Method of the same. An image sensor module structure comprising a substrate with a package receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate, and a package having a die with a micro lens disposed within the package receiving cavity. A dielectric layer is formed on the package and the substrate, a re-distribution conductive layer (RDL) is formed on the dielectric layer, wherein the RDL is coupled to the die and the conductive traces and the dielectric layer has an opening to expose the micro lens. A lens holder is attached on the substrate and the lens holder has a lens attached an upper portion of the lens holder. A filter is attached between the lens and the micro lens. The structure further comprises a passive device on the upper surface of the substrate within the lens holder.Type: ApplicationFiled: March 15, 2007Publication date: September 18, 2008Inventors: Wen-Kun Yang, Diann-Fang Lin, Jui-Hsien Chang, Tung-Chuan Wang
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Publication number: 20080197478Abstract: The present invention provides a semiconductor device package with the die receiving through hole and connecting through holes structure comprising a substrate with a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A die is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Further, a bonding wire is formed to couple and the bonding pads and the first contact pads. A dielectric layer is formed on the bonding wire, the die and the substrate.Type: ApplicationFiled: February 21, 2007Publication date: August 21, 2008Inventors: Wen-Kun Yang, Diann-Fang Lin, Tung-Chuan Wang, Hsien-Wen Hsu
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Publication number: 20080197435Abstract: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper layer of the substrate, wherein terminal pads are formed on the upper surface of the substrate, the same plain as the micro lens. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die. An opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for Image Sensor chip. A protection layer (film) be coated on the micro lens area with water repellent and oil repellent to away the particle contamination. A transparent cover with coated IR filter is optionally formed over the micron lens area for protection.Type: ApplicationFiled: February 21, 2007Publication date: August 21, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Tung-Chuan Wang
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Publication number: 20080191333Abstract: The present invention provides a structure of package comprising a substrate with a die through hole and a contact through holes structure formed there through, wherein a terminal pad is formed under the contact through hole structure and a contact pad is formed on a upper surface of the substrate. A die having a micro lens area is disposed within the die through hole by adhesion. A wire bonding is formed on the die and the substrate, wherein the wire bonding is coupled to the die and the contact pad. A protective layer is formed to cover the wire bonding. A transparent cover is disposed on the die within the die through hole by adhesion to expose the micro lens area. Conductive bumps are coupled to the terminal pads.Type: ApplicationFiled: February 8, 2007Publication date: August 14, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Diann-Fang Lin, Jui-Hsien Chang, Tung-chuan Wang, Hsien-Wen Hsu
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Publication number: 20080173792Abstract: The present invention provides an image sensor module structure comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate and a die having a micro lens disposed within the die receiving cavity. A dielectric layer is formed on the die and the substrate, a re-distribution conductive layer (RDL) is formed on the dielectric layer, wherein the RDL is coupled to the die and the conductive traces and the dielectric layer has an opening to expose the micro lens. A lens holder is attached on the substrate and the lens holder has a lens attached an upper portion of the lens holder. A filter is attached between the lens and the micro lens. The structure further comprises a passive device on the upper surface of the substrate within the lens holder.Type: ApplicationFiled: January 23, 2007Publication date: July 24, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Tung-chuan Wang, Chihwei Lin, Hsien-Wen Hsu
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Publication number: 20080157312Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die having micro lens area disposed within the die receiving through hole; a transparent cover covers the micro lens area; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Wen-Kun Yang, Jui-Hsien Chang, Tung-Chuan Wang
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Publication number: 20080142946Abstract: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the redistribution built up layer. Terminal Conductive bumps are coupled to the UBM.Type: ApplicationFiled: December 13, 2006Publication date: June 19, 2008Inventors: Wen-Kun Yang, Tung-Chuan Wang, Chao-Nan Chou, Chih-Wei Lin