Abstract: A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

Abstract: A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

Abstract: A method of forming a bump structure through the use of an electroplating solution, comprising the following steps. A substrate having an overlying conductive structure is provided. A patterned dry film resist is formed over the conductive structure. The patterned dry film resist having a trench exposing a portion of conductive structure. The patterned dry film resist adhering to the conductive structure at an interface. The structure is treated with a treatment that increases the adherence of the patterned dry film resist to the conductive structure at the interface. A conductive plug is over the exposed portion of the conductive structure within the trench through the use of the electroplating solution. The increased adhesion of the patterned dry film resist to the conductive structure at the interface preventing the electroplating solution from penetrating the interface of the patterned dry film resist and the conductive structure during the formation of the conductive plug.

Abstract: A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

Abstract: A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad.

Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad.