Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a semiconductor substrate, a first well region, first, second and third doped regions, and a gate structure. The first well region having a first conductivity type is located in the semiconductor substrate. The first and second doped region having a second conductivity type are located on the first well region. The third doped region having the first conductivity type is located on the first well region. The second and third doped regions are located on opposite sides of the first doped region. The gate structure is disposed on a portion of the semiconductor substrate between the first and second doped regions. A conductivity type of the gate structure is different from a conductivity type of the first and second doped regions. The gate structure is electrically connected to the first and third doped regions.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a gate structure and a first well region. The gate structure is disposed on the semiconductor substrate. The first well region having a first conductivity type is located in the semiconductor substrate. The first well region overlaps the gate structure. A first bottom of the first well region has a wave bottom surface.

Abstract: A die-level parametric prediction boosting method includes acquiring a wafer map having a plurality of dies, selecting a die from the plurality of dies, inputting physical location parametric data of the die and a plurality of electrical parametric features of the die to a training model, and generating predicted data of the die by the training model according to the physical location parametric data and the plurality of electrical parametric features.

Abstract: A die-level parametric prediction boosting method includes acquiring mass production data of a plurality of dies, identifying a comprehensive indicator of each die according to the mass production data, generating a wafer map distribution of the plurality of dies according to a plurality of comprehensive indicators, partitioning the plurality of dies into at least two die clustering groups, and inputting a plurality of electrical parametric features of each die clustering group to a training model for generating predicted data of each die clustering group.

Abstract: A cross-die interconnection monitor method includes providing a first die and a second die, embedding an intra-die detector into the first die for detecting a first feature of the first die, allocating a first inter-die detector from the first die to the second die for detecting a second feature between the first die and the second die, and comparing the first feature with the second feature for generating cross-die interconnect data from the first die to the second die by a neural network.

Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a semiconductor substrate, first and second well regions, and first and second heavily doped regions. The first and second well regions have a first conductivity type and are located in the semiconductor substrate. The first heavily doped region on the first well region has a second conductivity type. A first bottom of the first well region and a second bottom of the second well region are connected to each other and have different profiles. The first and second well regions have different doping concentrations. The second heavily doped region on the second well region has the first conductivity type. The first and second heavily doped regions are arranged side-by-side and are spaced apart from each other. The first heavily doped region is electrically connected to an input/output terminal.

Abstract: In an aspect of the disclosure, a method for detecting outlier integrated circuits on a wafer is provided. The method comprises: operating multiple test items for each IC on the wafer to generate measured values of the multiple test items for each IC; selecting a target IC and neighboring ICs on the wafer repeatedly. each time after selecting the target IC executes the following steps: selecting a measured value of the target IC as a target measured value and selecting measured values of the target IC and the neighboring ICs as feature values of the target IC and the neighboring ICs; executing a transformer deep learning model to generate a predicted value of the target measured value; and identifying outlier ICs according to the predicted values of all the target ICs and the corresponding target measured values of all the target ICs.

Abstract: An adaptive minimum voltage aging margin prediction method includes acquiring characteristic data of a plurality of dies in a testing line, predicting a wear-out failure rate of each module of the plurality of dies according to the characteristic data by using a neural network, and predicting a minimum voltage aging margin of the each module according to the wear-out failure rate of the each module by using the neural network.

Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a P-type semiconductor substrate, P-type and N-type well regions, a deep N-type well region, first N-type and P-type doped regions, second N-type and P-type doped regions. The P-type and N-type well regions are located in the P-type semiconductor substrate. The deep N-type well region is located in the P-type semiconductor substrate and below the P-type well region. The first N-type and P-type doped regions are located on the P-type well region. The second N-type and P-type doped regions are located on the N-type well region. The first P-type doped region is electrically connected to the second N-type doped region.

Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: A die-level electrical parameter extraction method includes: obtaining electrical parameters of a plurality of transistor types; obtaining measurement results of a plurality of logic blocks; estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks; and regarding a specific die of a wafer, obtaining die-level measurement of the plurality of logic blocks, and generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

Abstract: A dummy fill element for positioning inside an active inductor component of an integrated circuit (IC), the inductor component, the IC and a related method, are disclosed. The active inductor component is configured to convert electrical energy into magnetic energy to reduce parasitic capacitance in an IC. The dummy fill element includes: a first conductive incomplete loop having a first end and a second end, and a second conductive incomplete loop having a first end and a second end. First ends of the first and second conductive incomplete loops are electrically connected, and the second ends of the first and second conductive incomplete loops are electrically connected. In this manner, eddy currents created in each conductive incomplete loop by the magnetic energy cancel at least a portion of each other, allowing for a desired metal fill density and maintaining the inductor's Q-factor.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.

Abstract: A method of fabricating a semiconductor device is provided, which includes providing a plurality of fins over a substrate and forming a plurality of first gate structures having a first gate pitch and a plurality of second gate structures having a second gate pitch traversing across a first and a second set of fins, respectively. The second gate pitch is wider than the first gate pitch. Epitaxial regions are formed between adjacent second gate structures in the second set of fins. A dielectric layer is deposited over the second gate structures and the epitaxial regions. Contact openings are formed in the dielectric layer. At least one of the contact openings is formed over the second gate structure where the second gate structure traverses across the second set of fins. The contact openings are filled with a conductive material to form contact structures electrically coupled to the second gate structures.