Patents by Inventor Tung-Liang Shao

Tung-Liang Shao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210384103
    Abstract: A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.
    Type: Application
    Filed: August 25, 2021
    Publication date: December 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Liang SHAO, Jen-Yu WANG, Chung-Jung WU, Chih-Hang TUNG, Chen-Hua YU
  • Publication number: 20210375766
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
  • Publication number: 20210375724
    Abstract: A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Liang SHAO, Wen-Lin SHIH, Su-Chun YANG, Chih-Hang TUNG, Chen-Hua YU
  • Publication number: 20210335750
    Abstract: A chip package structure is provided. The chip package structure includes a first redistribution layer having a bonding portion. The bonding portion includes a dielectric layer. The chip package structure includes a chip structure bonded to the bonding portion. A first width of the dielectric layer of the bonding portion is substantially equal to a second width of the chip structure. The chip package structure includes a protective layer over the first redistribution layer and surrounding the chip structure. A portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang TUNG, Tung-Liang SHAO, Su-Chun YANG, Geng-Ming CHANG, Chen-Hua YU
  • Patent number: 11107747
    Abstract: A semiconductor package is provided. The semiconductor package includes a substrate and a semiconductor die over the substrate. A heat-dissipating feature covers the substrate and the semiconductor die, and a composite thermal interface material (TIM) structure is thermally bonded between the semiconductor die and the heat-dissipating feature. The composite TIM structure includes a metal-containing matrix material layer and polymer particles embedded in the metal-containing matrix material layer.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Liang Shao, Jen-Yu Wang, Chung-Jung Wu, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 11101195
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Liang Shao, Wen-Lin Shih, Su-Chun Yang, Chih-Hang Tung, Chen-Hua Yu
  • Publication number: 20210225788
    Abstract: Present disclosure provides a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate, a conductive layer in the substrate, a conductive bump over the substrate and electrically coupled to the conductive layer, and a dielectric stack, including a polymer layer laterally surrounding the conductive bump and including a portion spaced from a nearest outer edge of the conductive bump with a gap, wherein a first thickness of the polymer layer in a first region is greater than a second thickness of the polymer layer in a second region adjacent to the first region, a first bottom surface of the polymer layer in the first region is leveled with a second bottom surface of the polymer layer in the second region, and a dielectric layer underneath the polymer layer.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Inventors: CHANG-PIN HUANG, TUNG-LIANG SHAO, HSIEN-MING TU, CHING-JUNG YANG, YU-CHIA LAI
  • Patent number: 11056459
    Abstract: A method for forming a chip package structure is provided. The method includes partially removing a first redistribution layer to form an alignment trench in the first redistribution layer. The alignment trench surrounds a bonding portion of the first redistribution layer. The method includes forming a liquid layer over the bonding portion. The method includes disposing a chip structure over the liquid layer, wherein a first width of the bonding portion is substantially equal to a second width of the chip structure. The method includes evaporating the liquid layer. The chip structure is in direct contact with the bonding portion after the liquid layer is evaporated.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hang Tung, Tung-Liang Shao, Su-Chun Yang, Geng-Ming Chang, Chen-Hua Yu
  • Patent number: 10985121
    Abstract: Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chang-Pin Huang, Tung-Liang Shao, Hsien-Ming Tu, Ching-Jung Yang, Yu-Chia Lai
  • Publication number: 20210098336
    Abstract: An apparatus includes a semiconductor component and a cooling structure. The cooling structure is over a back side of the semiconductor component. The cooling structure includes a housing, a liquid delivery device and a gas exhaust device. The housing includes a cooling space adjacent to the semiconductor component. The liquid delivery device is connected to an inlet of the housing and is configured to deliver a liquid coolant into the cooling space from the inlet. The gas exhaust device is connected to an outlet of the housing and is configured to lower a pressure in the housing.
    Type: Application
    Filed: May 8, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Liang Shao, Lawrence Chiang Sheu, Chih-Hang Tung, Chen-Hua Yu, Yi-Li Hsiao
  • Publication number: 20210082849
    Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: TUNG-LIANG SHAO, YU-CHIA LAI, HSIEN-MING TU, CHANG-PIN HUANG, CHING-JUNG YANG
  • Publication number: 20210066164
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Application
    Filed: February 24, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Publication number: 20210050251
    Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.
    Type: Application
    Filed: May 5, 2020
    Publication date: February 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang
  • Patent number: 10879198
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • Patent number: 10854564
    Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Liang Shao, Yu-Chia Lai, Hsien-Ming Tu, Chang-Pin Huang, Ching-Jung Yang
  • Patent number: 10854580
    Abstract: The present disclosure provides a semiconductor structure including a first chip having a first dielectric surface, a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, and an air gap between the second dielectric surface and the first dielectric surface. The first chip includes a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines each having a sidewall partially exposed from the first dielectric surface. The present disclosure further provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Heng Lin, Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu
  • Publication number: 20200365550
    Abstract: A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chen-Hua Yu, Tung-Liang Shao, Chih-Hang Tung
  • Patent number: 10825804
    Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Pin Huang, Hsien-Ming Tu, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai
  • Patent number: 10734348
    Abstract: A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tung-Liang Shao, Chih-Hang Tung
  • Publication number: 20200098720
    Abstract: A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventors: Chen-Hua Yu, Tung-Liang Shao, Chih-Hang Tung