Abstract: Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

Abstract: The present disclosure relates to a heat sink pedestal including a composite material. The composite material may include at least one layer of a thermally conductive primary material and at least one layer of a thermally conductive secondary material. The composite material may include a conductivity ratio of lateral thermal conductivity (Kz) to planar thermal conductivity (Kx, Ky) of the composite material of at least 0. The heat sink pedestal may be conformable to a shape of a semiconductor chip.

Abstract: The present disclosure relates to a heat sink pedestal including a composite material. The composite material may include at least one layer of a thermally conductive primary material and at least one layer of a thermally conductive secondary material. The composite material may include a conductivity ratio of lateral thermal conductivity (Kz) to planar thermal conductivity (Kx, Ky) of the composite material of at least 0. The heat sink pedestal may be conformable to a shape of a semiconductor chip.

Abstract: System and techniques for abandoned object detection are described herein. a fence is established about a person and an object is detected within the fence. An entry is created in an object-person relationship data structure to establish a relationship between the person and the object within the fence. Then, the position of the object is monitored until an indication that the fence is terminated is received. If it is detected that the object is outside the fence during the monitoring, the person is alerted.

Abstract: Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

Abstract: An apparatus to implement an IP independent firmware load is disclosed. The apparatus includes a plurality of agents, a plurality of agents, at least one agent including a memory to store firmware to be executed by the agent to perform a function associated with the agent and a register to store enumeration data for the firmware load mechanism of the IP, and a processor to initiate an enumeration process to read the enumeration data from the register of the at least one agent, make a decision based on that data to retrieve a firmware module from a storage device, verify the firmware module, and load the firmware module into the memory of the at least one agent.

Abstract: Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

Abstract: Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

Abstract: Various embodiments are generally directed to techniques for computing platform initialization, such as by utilizing a field programmable gate array (FPGA) to initialize one or more dependent bootable components (DPCs) of the computing platform, for instance. In one or more embodiments, the FPGA may be reconfigured to perform a runtime operation after initialization of the computing platform. In embodiments described herein, a DPC may include initialization of any hardware or software components of a computing platform, such as silicon components and platform components. In such embodiments, a boot sequence may include boot instructions to initialize a set of DPCs. In some such embodiments, the boot sequence may initialize the computing platform. In one or more embodiments, computing platform initialization may include preparing the computing platform to perform input/output (I/O) operations. In one or more such embodiments, the I/O operations may be performed via an operating system.

Abstract: Apparatus, systems, or methods for a programmable circuit to facilitate a processor to boot a computing device having the processor. A programmable circuit may include non-volatile storage and firmware stored in the non-volatile storage. The firmware may configure the programmable circuit as a memory controller of a memory device coupled to the programmable circuit, to facilitate the processor to boot the computing device having the processor, the programmable circuit, and the memory device, into operation. Other embodiments may also be described and claimed.

Abstract: Apparatus, systems, or methods for a programmable circuit to facilitate a processor to boot a computing device having the processor. A programmable circuit may include non-volatile storage and firmware stored in the non-volatile storage. The firmware may configure the programmable circuit as a memory controller of a memory device coupled to the programmable circuit, to facilitate the processor to boot the computing device having the processor, the programmable circuit, and the memory device, into operation. Other embodiments may also be described and claimed.