Abstract: A multi-link device includes a first link queue, a second link queue, a control circuit, a first transmitter and a second transmitter. The control circuit includes a common queue for buffering a plurality of packets, each packet having a sequence number. The control circuit obtains a minimum sequence number of all packets in the first link queue and the second link queue, computes a maximum sequence number according to the minimum sequence number and a block acknowledgment window size, determines whether to allocate a set of packets from the common queue according to the maximum sequence number, and if so, allocates the set of packets to the first link queue and/or the second link queue. The first transmitter transmits a packet from the first link queue to a first receiving device, and the second transmitter transmits a packet from the second link queue to a second receiving device.

Abstract: A multi-link device includes a first link queue, a second link queue, a control circuit, a first transmitter and a second transmitter. The control circuit includes a common queue for buffering a plurality of packets, each packet having a sequence number. The control circuit obtains a minimum sequence number of all packets in the first link queue and the second link queue, computes a maximum sequence number according to the minimum sequence number and a block acknowledgment window size, determines whether to allocate a set of packets from the common queue according to the maximum sequence number, and if so, allocates the set of packets to the first link queue and/or the second link queue. The first transmitter transmits a packet from the first link queue to a first receiving device, and the second transmitter transmits a packet from the second link queue to a second receiving device.

Abstract: A data decryption system includes an address checking circuit, an encryption/decryption processor, and a computation circuit. The address checking circuit is configured to receive an address through an address channel. The computation circuit is coupled to the encryption/decryption processor. The computation circuit is configured to receive a reading data of the address from a storage device through a data channel in a first duration. The encryption/decryption processor computes a second key in a second duration, according to a first key and the address, and the second key is configured to decrypt the reading data, wherein the first duration overlaps with the second duration.

Abstract: A data decryption system includes an address checking-circuit, an encryption/decryption processor, and a computation circuit. The address checking circuit is configured to receive an address through an address channel. The computation circuit is coupled to the encryption/decryption processor. The computation circuit is configured to receive a reading data of the address from a storage device through a data channel in a first duration. The encryption/decryption processor computes a second key in a second duration, according to a first key and the address, and the second key is configured to decrypt the reading data, wherein the first duration overlaps with the second duration.