Abstract: Formulations and methods of making solar cells are disclosed. In general, the invention presents a solar cell contact made from a mixture wherein the mixture comprises a solids portion and an organics portion, wherein the solids portion comprises from about 85 to about 99 wt % of a metal component, and from about 1 to about 15 wt % of a lead-free glass component. Both front contacts and back contacts are disclosed.

Abstract: An apparatus, a method, and a computer program product are provided for identifying signals in analogue electrical systems. The ID select signals that control the timing of this signal identification circuit comprise sequential numbers that count up and identify a corresponding signal. The signals to be identified are located on a group of input/output (I/O) pins. One multiplexer (first) selects a specific I/O pin in response to the ID select signals. An isolated voltage source is connected to this multiplexer and provides the selected signal to another multiplexer (second). The second multiplexer switches from this isolated voltage source to ground potential in response to the ID select signals. The isolated voltage source floats at the DC level of the selected I/O driver pin. Therefore, by connecting to the selected signal's I/O pin and the output of the second multiplexer, the selected signal can be identified and then probed.

Abstract: Formulations and methods of making solar cells are disclosed. In general, the invention presents a solar cell contact made from a mixture wherein the mixture comprises a solids portion and an organics portion, wherein the solids portion comprises from about 85 to about 99 wt % of silver, and from about 1 to about 15 wt % of a glass component wherein the glass component comprises from about 15 to about 75 mol % PbO, and from about 5 to about 50 mol % SiO2, and preferably with no B2O3.

Abstract: An apparatus for managing refrigerant charge in an air conditioning unit comprising a cooling circuit through which a refrigerant flows from a compressor, through a condenser, and through an evaporator, a heat recovery circuit extending from a first terminus between the compressor and the condenser to a second terminus between the evaporator and the condenser, a heat recovery unit located between the first and second terminus of the heat recovery circuit, a first valve located between the condenser and the first terminus, a second valve located between the first terminus and the heat recovery unit, a third valve located on a cooling charge circuit having a first end on the cooling circuit between the condenser and the evaporator and a second end at the evaporator, a fourth valve located on a heating charge circuit having a first end on the heat recovery circuit and a second end at the evaporator, and a logic unit for sensing a saturated temperature and opening and closing the valves based upon the saturated t

Abstract: A method for controlling load capacity in an air conditioning unit comprising the steps of initializing a saturated condensing temperature upper bound (SCT_UP), comparing a saturated condensing temperature (SCT) to a maximum condensing temperature threshold (MCT_TH), unloading a single load capacity step, allowing the air conditioning unit to stabilize, and setting the SCT_UP equal to the SCT after the unloading, and increasing the load capacity by one capacity step if increased load capacity is required, the SCT is less than or equal to the MCT_TH, and the SCT<the SCT_UP.

Abstract: A method for controlling load capacity in an air conditioning unit comprising the steps of initializing a saturated condensing temperature upper bound (SCT_UP), comparing a saturated condensing temperature (SCT) to a maximum condensing temperature threshold (MCT_TH), unloading a single load capacity step, allowing the air conditioning unit to stabilize, and setting the SCT_UP equal to the SCT after the unloading, and increasing the load capacity by one capacity step if increased load capacity is required, the SCT is less than or equal to the MCT_TH, and the SCT<the SCT_UP.

Abstract: The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. The processor is coupled to the controller and configured to generate self-identify control signals and to transmit the self-identify control signals to the controller.

Abstract: A method and an apparatus are provided for reducing scan power consumption when unloading and restoring content of a processor. The processor has one or more scan chains. First, at least one scan chain is partitioned into a plurality of segments. Second, one of the segments is scanned at a time.

Abstract: An expansion valve is controlled in response to sensing conditions at the outlet of at least one compressor within a refrigeration loop in a manner that achieves low suction superheat operation of the compressor. In particular, a discharge superheat is computed using data obtained from a specific mathematical model of the compression process corresponding to the current capacity stage of the compressor. The position of the expansion valve is controlled so as to result in an actual discharge superheat being within a predetermined dead band amount of the computed discharge superheat.

Abstract: An electronic expansion valve (EXV) used in a refrigeration cycle for a heat pump or chiller is controlled to maintain minimum pinch for ensuring proper flooded cooler exchange performance by monitoring the delta temperature between the cooler fluid and the saturated suction temperature. The discharge superheat is monitored to protect the compressor from liquid slugging. If the discharge superheat is lower than the expected value, the EXV opening is adjusted. A controller monitors certain system variables which are used to determine the optimal position of the EXV to optimize the system performance, the proper discharge superheat value, and the appropriate refrigerant charge.

Abstract: A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has an associated cache control system. When a processor's cache control system does not have a required memory location in the cache memory, it broadcasts a memory request packet across the memory bus for the required data. If an owned cache line is being replaced, the cache control system copies the old cache line data to the pending write-back cache controller which is responsible for the write-backs of owned cache lines to main memory. The cache control system then transfers ownership of the old replaced cache line to the pending write-back controller.

Abstract: A method is provided for forming metallizations on a semiconductor component, which are closer together than is possible with the present day masking technology.In accordance with the invention, a pattern of minimum dimensions is defined in a mask by means of two openings. This pattern is underetched, either by light over-exposure, or by particle back-scattering. Two metallizations are deposited, directionally in the bottom of the openings then a dielectric layer is deposited, non directionally, on the metallizations, the mask is removed by dissolution.

Abstract: The logic circuit comprises two field effect transistors in series, whose gates are connected to the supply voltage by a first load. The source of the first field effect transistor is connected to earth. The drain of the second field effect transistor is connected on the one hand to the supply voltage by a second load and to the gate of a third field effect transistor, whose drain is connected to the supply voltage and whose source is connected to the common point constituted by the drain of the first field effect transistor and the source of the second field effect transistor via a Schottky diode.

Abstract: A high-speed logic inverter, in the form of an integrated circuit, with a single supply source, using field-effect transistors of the "quasi-normally-off" type, and the logic operators having several inputs and several outputs which derive therefrom.One embodiment of the invention starts from an inverter with input, through a diode, on a field-effect transistor gate, and with its output at the source of a field-effect transistor. This basic diagram is added to by providing the input (between supply pole and input terminal) with two pairs of diodes ending at the gates of a dual-gate transistor, and by providing independent outputs obtained by connecting the common drain connected transistor gates to the supply pole distinct from ground.