Abstract: A display driver for driving a display device including a pixel array is provided. The display driver includes a plurality of driving channels. The driving channels is configured to output driving signals in a pulse width modulation manner to drive the pixel array to illuminate in a first frame period which is being divided into a plurality of subframe periods. A first driving channel of the plurality of driving channels outputs a first driving signal in a first subframe period combination. A second driving channel of the plurality of driving channels outputs a second driving signal in a second subframe period combination different than the first subframe period combination. Each of the first subframe period combination and the second subframe period combination comprises at least one subframe period of the first frame period.

Abstract: A display driver for driving a display device including a pixel array is provided. The display driver includes a plurality of driving channels. The driving channels is configured to output driving signals in a pulse width modulation manner to drive the pixel array to illuminate in a first frame period which is being divided into a plurality of subframe periods. A first driving channel of the plurality of driving channels outputs a first driving signal in a first subframe period combination. A second driving channel of the plurality of driving channels outputs a second driving signal in a second subframe period combination different than the first subframe period combination. Each of the first subframe period combination and the second subframe period combination comprises at least one subframe period of the first frame period.

Abstract: A display device includes a timing control circuit and a data driving circuit. The data driving circuit receives the first clock embedded training data from the timing control circuit, performs a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a first clock signal, and receives the first clock embedded image data from the timing control circuit. The data driving circuit also receives a second clock embedded training data from the timing control circuit, performs a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a second clock signal, and receives the second clock embedded image data from the timing control circuit. The frequency of the first clock signal is different from a frequency of the second clock signal.

Abstract: A display device includes a timing control circuit, a first data driving circuit, and a second data driving circuit. The first data driving circuit receives the first clock embedded training data from the timing control circuit, performs a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a first clock signal, and receives the first clock embedded image data from the timing control circuit. The second data driving circuit receives a second clock embedded training data from the timing control circuit, performs a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a second clock signal, and receives the second clock embedded image data from the timing control circuit. The frequency of the first clock signal is different from that of the second clock signal.

Abstract: A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register.

Abstract: A display device includes a timing control circuit and a data driving circuit. The data driving circuit receives the first clock embedded training data from the timing control circuit, performs a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a first clock signal, and receives the first clock embedded image data from the timing control circuit. The data driving circuit also receives a second clock embedded training data from the timing control circuit, performs a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a second clock signal, and receives the second clock embedded image data from the timing control circuit. The frequency of the first clock signal is different from a frequency of the second clock signal.

Abstract: A display device includes a timing control circuit, a first data driving circuit, and a second data driving circuit. The first data driving circuit receives the first clock embedded training data from the timing control circuit, performs a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a first clock signal, and receives the first clock embedded image data from the timing control circuit. The second data driving circuit receives a second clock embedded training data from the timing control circuit, performs a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a second clock signal, and receives the second clock embedded image data from the timing control circuit. The frequency of the first clock signal is different from that of the second clock signal.

Abstract: A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register.

Abstract: A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register.

Abstract: An interface circuit for a serial bus is disclosed and includes a receiving terminal, an output terminal, a first switching circuit, a voltage source, and a second switching circuit. The receiving and output terminals are used for receiving an input signal and outputting a first voltage signal respectively. The first switching circuit is used for determining a coupling relationship between the output terminal and the grounded terminal according to difference between the input signal and a grounding voltage provided by the grounded terminal. The voltage source is used for producing a voltage drop based on a driving voltage driving the serial bus interface circuit to provide a first voltage. The second switching circuit is used for determining a coupling relationship between the first switching circuit and the voltage source according to difference between the input signal and the first voltage.

Abstract: A shift register circuit includes a plurality of bit register units, coupled in series, for transferring an input signal among the plurality of bit register units to sequentially output the input signal to a plurality of data output terminals according to a control signal and a clock signal, wherein the number of the plurality of data output terminals is greater than that of the plurality of bit register units, and a control unit for generating the control signal to control transference of the input signal.

Abstract: A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register.

Abstract: An interface circuit for a serial bus is disclosed and includes a receiving terminal, an output terminal, a first switching circuit, a voltage source, and a second switching circuit. The receiving and output terminals are used for receiving an input signal and outputting a first voltage signal respectively. The first switching circuit is used for determining a coupling relationship between the output terminal and the grounded terminal according to difference between the input signal and a grounding voltage provided by the grounded terminal. The voltage source is used for producing a voltage drop based on a driving voltage driving the serial bus interface circuit to provide a first voltage. The second switching circuit is used for determining a coupling relationship between the first switching circuit and the voltage source according to difference between the input signal and the first voltage.

Abstract: A shift register circuit includes a plurality of bit register units, coupled in series, for transferring an input signal among the plurality of bit register units to sequentially output the input signal to a plurality of data output terminals according to a control signal and a clock signal, wherein the number of the plurality of data output terminals is greater than that of the plurality of bit register units, and a control unit for generating the control signal to control transference of the input signal.

Abstract: A configurable voltage generator is disclosed for generating multiple levels of output. It includes an oscillator module for generating a pumping signal, a digital to analog (D/A) converter coupled to the oscillator for generating one or more analog signals of a predetermined voltage level based on the pumping signal as configured by a set of inputs thereof, and a charge pump coupled to the D/A converter for producing a direct current (DC) output based on the analog signals generated by the D/A converter.