Patents by Inventor Tung-Wang Huang

Tung-Wang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955191
    Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Perng-Fei Yuh, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee, Yih Wang
  • Patent number: 6867089
    Abstract: A method of forming a bottle-shaped trench for capacitor in a semiconductor substrate. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. Then, an oxide film is formed on the top portion of the trench. Next, a rugged polysilicon layer is formed on the bottom portion and the top portion of the trench. The rugged polysilicon layer and the semiconductor substrate are etched through the bottom portion of the trench by diluted ammonia solution as the etchant to form a bottle-shaped trench having a rugged surface. Next, the oxide film is removed.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: March 15, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Yi-Nan Chen, Tung-Wang Huang, Hsin-Jung Ho, Hsien-Wen Liu
  • Patent number: 6770563
    Abstract: A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the sidewall of the upper portion of the trench. A spacer is formed on the sidewall. The residual dielectric layer in the trench is removed, and the partial trench not covered by the spacer is etched to a bottle shape.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: August 3, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Tung-Wang Huang, Chang Rong Wu, Chien-Mao Liao, Hsin-Jung Ho
  • Patent number: 6743728
    Abstract: A method for forming shallow trench isolation. A substrate is provided with a mask layer formed thereon. The mask layer is etched to expose a portion of the substrate, and the portion of the substrate is etched to form a trench. A liner layer is formed on the inside wall of the trench. A first dielectric layer and a sacrificial layer are sequentially deposited on the substrate such that the trench is substantially filled, wherein the first dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). Portions of the first dielectric layer and the sacrificial layer are removed from the trench. A second dielectric layer is deposited on the substrate such that the trench is substantially filled, wherein the second dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). A portion of the second dielectric layer is removed from the trench.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: June 1, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Tzu En Ho, Chang Rong Wu, Tung-Wang Huang, Shing-Yih Shih
  • Publication number: 20040058549
    Abstract: A method for forming shallow trench isolation. A substrate is provided with a mask layer formed thereon. The mask layer is etched to expose a portion of the substrate, and the portion of the substrate is etched to form a trench. A liner layer is formed on the inside wall of the trench. A first dielectric layer and a sacrificial layer are sequentially deposited on the substrate such that the trench is substantially filled, wherein the first dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). Portions of the first dielectric layer and the sacrificial layer are removed from the trench. A second dielectric layer is deposited on the substrate such that the trench is substantially filled, wherein the second dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). A portion of the second dielectric layer is removed from the trench.
    Type: Application
    Filed: December 17, 2002
    Publication date: March 25, 2004
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Tzu En Ho, Chang Rong Wu, Tung-Wang Huang, Shing-Yih Shih
  • Publication number: 20040053464
    Abstract: A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the sidewall of the upper portion of the trench. A spacer is formed on the sidewall. The residual dielectric layer in the trench is removed, and the partial trench not covered by the spacer is etched to a bottle shape.
    Type: Application
    Filed: January 3, 2003
    Publication date: March 18, 2004
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Tung-Wang Huang, Chang-Rong Wu, Chien-Mao Liao, Hsin-Jung Ho
  • Patent number: 6693006
    Abstract: A method for increasing area of a trench capacitor. First, a first oxide layer and a first nitride layer are sequentially formed on a substrate. An opening is formed through the first oxide layer and the first nitride layer into the substrate. A part of the first oxide layer exposed in the opening is removed to form a first recess, and then a second nitride layer is formed therein. A second oxide layer is formed in the lower portion of the opening. After a third nitride layer is formed in the upper portion of the opening, the second oxide layer is removed. The substrate in the opening is etched using the first nitride layer, the second nitride layer and the third nitride layer as a mask to form a second recess in the lower portion of the opening. The second nitride layer and the third nitride layer are then removed.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: February 17, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Hsin-Jung Ho, Chang Rong Wu, Yi-Nan Chen, Tung-Wang Huang
  • Publication number: 20030153158
    Abstract: A method for increasing area of a trench capacitor. First, a first oxide layer and a first nitride layer are sequentially formed on a substrate. An opening is formed through the first oxide layer and the first nitride layer into the substrate. A part of the first oxide layer exposed in the opening is removed to form a first recess, and then a second nitride layer is formed therein. A second oxide layer is formed in the lower portion of the opening. After a third nitride layer is formed in the upper portion of the opening, the second oxide layer is removed. The substrate in the opening is etched using the first nitride layer, the second nitride layer and the third nitride layer as a mask to form a second recess in the lower portion of the opening. The second nitride layer and the third nitride layer are then removed.
    Type: Application
    Filed: December 17, 2002
    Publication date: August 14, 2003
    Applicant: Nanya Technology Corporation
    Inventors: Hsin-Jung Ho, Chang Rong Wu, Yi-Nan Chen, Tung-Wang Huang
  • Publication number: 20030143802
    Abstract: A method of forming a bottle-shaped trench for capacitor in a semiconductor substrate. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. Then, an oxide film is formed on the top portion of the trench. Next, a rugged polysilicon layer is formed on the bottom portion and the top portion of the trench. The rugged polysilicon layer and the semiconductor substrate are etched through the bottom portion of the trench by diluted ammonia solution as the etchant to form a bottle-shaped trench having a rugged surface. Next, the oxide film is removed.
    Type: Application
    Filed: September 24, 2002
    Publication date: July 31, 2003
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Nan Chen, Tung-Wang Huang, Hsin-Jung Ho, Hsien-Wen Liu