Abstract: A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region.

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

Abstract: An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.

Abstract: A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region.

Abstract: An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

Abstract: A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region.

Abstract: A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region.

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

Abstract: The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.