Patents by Inventor Tung-Yen Lai

Tung-Yen Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thin film transistor and fabricating method
    Patent number: 8987071
    Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 24, 2015
    Assignee: National Applied Research Laboratories
    Inventors: Min-Cheng Chen, Chang-Hsien Lin, Chia-Yi Lin, Tung-Yen Lai, Chia-Hua Ho
  • THIN FILM TRANSISTOR AND FABRICATING METHOD
    Publication number: 20140099756
    Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.
    Type: Application
    Filed: December 16, 2013
    Publication date: April 10, 2014
    Applicant: National Applied Research Laboratories
    Inventors: Min-Cheng CHEN, Chang-Hsien LIN, Chia-Yi LIN, Tung-Yen LAI, Chia-Hua HO
  • THIN FILM TRANSISTOR AND FABRICATING METHOD
    Publication number: 20130161755
    Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.
    Type: Application
    Filed: April 19, 2012
    Publication date: June 27, 2013
    Applicant: National Applied Research Laboratories
    Inventors: Min-Cheng Chen, Chang-Hsien Lin, Chia-Yi Lin, Tung-Yen Lai, Chia-Hua Ho