Patents by Inventor Tung Yi Chou

Tung Yi Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Co-fired multi-layer stack chip resistor and manufacturing method
    Patent number: 8451085
    Abstract: A co-fired multi-layer stack chip resistor is provided. The co-fired multi-layer stack chip resistor includes a ceramic substrate and a multi-layer stack resistance structure monomer. The ceramic substrate is formed by stacking multiple layers of the ceramic membranes, wherein the ceramic membranes is formed of a bearing membrane and a porcelain slurry with the solvent, the binder and the dispersant. The multi-layer stack resistance structure monomer is stacked on the ceramic substrate, and includes multiple bearing membranes and multiple resistive layers, wherein each resistive layer is formed on the surface of the corresponding bearing membrane, the resistive layers are parallel to each other, and the contiguous resistive layers are stacked with the interval of the predetermined distance along the vertical direction.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: May 28, 2013
    Assignee: Prosperity Dielectrics Co., Ltd.
    Inventors: Yung Cheng Tsai, Ching Jen Tsai, Tung Yi Chou, Hung Chun Wu
  • CO-FIRED MULTI-LAYER STACK CHIP RESISTOR AND MANUFACTURING METHOD
    Publication number: 20130127587
    Abstract: A co-fired multi-layer stack chip resistor is provided. The co-fired multi-layer stack chip resistor includes a ceramic substrate and a multi-layer stack resistance structure monomer. The ceramic substrate is formed by stacking multiple layers of the ceramic membranes, wherein the ceramic membranes is formed of a bearing membrane and a porcelain slurry with the solvent, the binder and the dispersant. The multi-layer stack resistance structure monomer is stacked on the ceramic substrate, and includes multiple bearing membranes and multiple resistive layers, wherein each resistive layer is formed on the surface of the corresponding bearing membrane, the resistive layers are parallel to each other, and the contiguous resistive layers are stacked with the interval of the predetermined distance along the vertical direction.
    Type: Application
    Filed: June 21, 2012
    Publication date: May 23, 2013
    Applicant: PROSPERITY DIELECTRICS CO., LTD.
    Inventors: YUNG CHENG TSAI, CHING JEN TSAI, TUNG YI CHOU, HUNG CHUN WU