Patents by Inventor Tung-Ying Lee
Tung-Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250142919Abstract: A semiconductor device includes a channel structure, source region, a drain region, metal gate structure, and a self-assembled layer. The source region and the drain region are on opposite sides of the channel structure. A bottom surface of the source region is lower than a bottom surface of the channel structure, and a top surface of the source region is higher than a top surface of the channel structure. The metal gate structure covers the channel structure and between the source region and the drain region. The self-assembled layer is between the source region and the metal gate structure. The self-assembled layer is in contact with the bottom surface of the channel structure but spaced apart from the top surface of the channel structure.Type: ApplicationFiled: January 3, 2025Publication date: May 1, 2025Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITYInventors: Tung-Ying LEE, Tse-An CHEN, Tzu-Chung WANG, Miin-Jang CHEN, Yu-Tung YIN, Meng-Chien YANG
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Publication number: 20250126842Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.Type: ApplicationFiled: December 19, 2024Publication date: April 17, 2025Inventors: Tung Ying Lee, Kai-Tai Chang, Meng-Hsuan Hsiao
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Publication number: 20250126881Abstract: A semiconductor structure is provided. The semiconductor structure includes a first active region and a second active region adjacent to the first active region, a first gate stack extending across the first active region in a first direction, an isolation feature extending across the second active region in the first direction; and a first gate-cut feature sandwiched between the first gate stack and the isolation feature.Type: ApplicationFiled: December 18, 2024Publication date: April 17, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun NG, Yu-Chao LIN, Tung-Ying LEE
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Publication number: 20250118345Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.Type: ApplicationFiled: December 16, 2024Publication date: April 10, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Win-San KHWA, Ping-Chun WU, Tung Ying LEE, Meng-Fan CHANG
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Patent number: 12256654Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. An extending direction of a sidewall of the storage element layer is different from an extending direction of a sidewall of the top electrode. A semiconductor device having the memory cell is also provided.Type: GrantFiled: November 20, 2023Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chao Lin, Tung-Ying Lee
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Patent number: 12249574Abstract: A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.Type: GrantFiled: January 14, 2022Date of Patent: March 11, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung Ying Lee, Bo-Jiun Lin
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Patent number: 12243930Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.Type: GrantFiled: July 27, 2022Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Tai Chang, Tung-Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
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Patent number: 12245526Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating. The protection coating forms a first interface with the phase change element. The first interface has a first slope at a first position and a second slope at a second position higher than the first position, the second slope is different from the first slope.Type: GrantFiled: September 27, 2023Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chao Lin, Yuan-Tien Tu, Shao-Ming Yu, Tung-Ying Lee
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Publication number: 20250072072Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a first transistor over a substrate, including a first channel layer over the substrate, a second channel layer over and spaced apart from the first channel layer in a first direction, and a first source/drain structure attached to the first channel layer and the second channel layer. The semiconductor structure further includes a second transistor over the substrate, including a third channel layer over the substrate, a fourth channel layer over and spaced apart from the third channel layer in the first direction, and a second source/drain structure attached to the third channel layer and the fourth channel layer. In addition, a dimension of the first source/drain structure in the first direction is different from a dimension of the second source/drain structure in the first direction.Type: ApplicationFiled: November 8, 2024Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Hsuan HSIAO, Winnie Victoria Wei-Ning CHEN, Tung Ying LEE
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Patent number: 12237375Abstract: A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.Type: GrantFiled: July 26, 2023Date of Patent: February 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Wei Shen, Tse-An Chen, Tung-Ying Lee, Lain-Jong Li
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Patent number: 12237421Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate, and a first gate structure formed over the first nanostructures. The semiconductor device structure includes a second gate structure formed over the second nanostructures, and the second gate structure includes a gate dielectric layer, a first type work function layer and a filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and the first isolation layer includes a first sidewall surface, and the first sidewall surface is in direct contact with a first interface between the gate dielectric layer and the first type work function layer and a second interface between the work function layer and the filling layer.Type: GrantFiled: February 15, 2024Date of Patent: February 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chao Lin, Wei-Sheng Yun, Tung-Ying Lee
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Publication number: 20250063770Abstract: A semiconductor device including a substrate, a semiconductor layer, a gate, a dielectric structure, and a source/drain structure is provided. The semiconductor layer is disposed on the substrate, and is made of a first low dimensional material. The gate is disposed on the substrate and overlaps the semiconductor layer. The dielectric structure is disposed on the semiconductor layer and includes a trench structure reaching a portion of the semiconductor layer. The source/drain structure includes a barrier layer made of a second low dimensional material continuously extending along the trench structure and a metal fill filling a volume surrounded by the barrier layer.Type: ApplicationFiled: August 16, 2023Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Jiun Lin, Tung-Ying Lee, Yu-Chao Lin
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Patent number: 12224334Abstract: A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.Type: GrantFiled: May 26, 2023Date of Patent: February 11, 2025Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITYInventors: Tung-Ying Lee, Tse-An Chen, Tzu-Chung Wang, Miin-Jang Chen, Yu-Tung Yin, Meng-Chien Yang
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Publication number: 20250048941Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.Type: ApplicationFiled: October 24, 2024Publication date: February 6, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chao Lin, Carlos H. Diaz, Shao-Ming Yu, Tung-Ying Lee
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Patent number: 12213388Abstract: A memory cell includes a bottom electrode, a first dielectric layer, a top electrode, and a variable resistance layer. The first dielectric layer laterally surrounds the bottom electrode. The top electrode is disposed over the bottom electrode and the first dielectric layer. The variable resistance layer is sandwiched between the bottom electrode and the top electrode and between the first dielectric layer and the top electrode. The variable resistance layer exhibits a T-shape in a cross-sectional view.Type: GrantFiled: September 21, 2023Date of Patent: January 28, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chao Lin, Tung-Ying Lee, Da-Ching Chiou
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Patent number: 12211844Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET.Type: GrantFiled: July 21, 2022Date of Patent: January 28, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Yu-Chao Lin, Tung-Ying Lee
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Publication number: 20250031381Abstract: A method of forming a semiconductor device is provided. A first ferroelectric inducing layer including Ru is deposited on a substrate. A ferroelectric layer including HfZrO is deposited on the first ferroelectric inducing layer. A second ferroelectric inducing layer including Ru is deposited on the ferroelectric layer, wherein the HfZrO of the ferroelectric layer is in physical contact with the Ru of the first ferroelectric inducing layer and the Ru of the second ferroelectric inducing layer. The second ferroelectric inducing layer, the ferroelectric layer and the first ferroelectric inducing layer are patterned.Type: ApplicationFiled: July 21, 2023Publication date: January 23, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Jiun Lin, Chih-Sheng Chang, Yu-Chao Lin, Tung-Ying Lee
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Patent number: 12205670Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.Type: GrantFiled: August 21, 2022Date of Patent: January 21, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Win-San Khwa, Ping-Chun Wu, Tung Ying Lee, Meng-Fan Chang
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Patent number: 12191304Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.Type: GrantFiled: May 22, 2023Date of Patent: January 7, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tung Ying Lee, Ziwei Fang, Yee-Chia Yeo, Meng-Hsuan Hsiao
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Publication number: 20250006800Abstract: A method of forming a semiconductor device comprises the following steps. A dielectric layer is formed over a substrate. A 2D material layer is formed over the dielectric layer. An adhesion layer is formed over the 2D material layer. Source/drain electrodes are formed on opposite sides of the adhesion layer. A first high-k gate dielectric layer is formed over the adhesion layer, wherein the adhesion layer has a material different from a material of the first high-k gate dielectric layer.Type: ApplicationFiled: July 1, 2023Publication date: January 2, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bo-Jiun LIN, Tsung-En LEE, Tung Ying LEE, Chao-Ching CHENG