Patents by Inventor Tung-Ying Lee

Tung-Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12376345
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanowire over a semiconductor fin. The semiconductor structure also includes a second nanowire over the first nanowire and a third nanowire over the second nanowire. The semiconductor structure further includes a source/drain wrapping around the first nanowire, the second nanowire and the third nanowire. A thickness of a first portion of the source/drain vertically sandwiched between the first nanowire and the second nanowire is different from a thickness of a second portion of the source/drain vertically sandwiched between the second nanowire and the third nanowire.
    Type: Grant
    Filed: May 22, 2024
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Hsuan Hsiao, Wei-Sheng Yun, Winnie Victoria Wei-Ning Chen, Tung Ying Lee, Ling-Yen Yeh
  • Patent number: 12369387
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: July 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 12349607
    Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • Publication number: 20250203978
    Abstract: A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.
    Type: Application
    Filed: February 25, 2025
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Wei Shen, Tse-An Chen, Tung-Ying Lee, Lain-Jong Li
  • Patent number: 12336192
    Abstract: A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.
    Type: Grant
    Filed: June 13, 2024
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Tung-Ying Lee, Yuan-Tien Tu, Jung-Piao Chiu
  • Patent number: 12327792
    Abstract: A semiconductor structure includes a substrate and an interconnect. The substrate has a semiconductor device. The interconnect is disposed over the substrate and electrically coupled to the semiconductor device, and includes a metallization layer and a capping layer. The metallization layer is disposed over the substrate and includes a via portion and a line portion connecting to the via portion. The capping layer covers the line portion, where the line portion is sandwiched between the via portion and the capping layer, and the capping layer includes a plurality of sub-layers.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: June 10, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Tung-Ying Lee
  • Patent number: 12324165
    Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.
    Type: Grant
    Filed: March 11, 2024
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Ming-Yuan Song, Yen-Lin Huang, Shy-Jay Lin, Tung-Ying Lee, Xinyu Bao
  • Patent number: 12324364
    Abstract: A memory device is provided. The memory device includes a bottom electrode, a first data storage layer, a second data storage layer, an interfacial conductive layer and a top electrode. The first data storage layer is disposed on the bottom electrode and in contact with the bottom electrode. The second data storage layer is disposed over the first data storage layer. The interfacial conductive layer is disposed between the first data storage layer and the second data storage layer. The top electrode is disposed over the second data storage layer.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Kai-Tai Chang, Hung-Li Chiang, Yu-Sheng Chen
  • Patent number: 12324214
    Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Tzu-Chung Wang
  • Patent number: 12324362
    Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.
    Type: Grant
    Filed: January 26, 2024
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung Ying Lee, Yu Chao Lin, Shao-Ming Yu
  • Publication number: 20250176442
    Abstract: A memory cell includes a bottom electrode, a top electrode, and a variable resistance layer. The top electrode is disposed over the bottom electrode. The variable resistance layer is sandwiched between the bottom electrode and the top electrode. A first portion of a bottom surface of the variable resistance layer and a second portion of the bottom surface of the variable resistance layer are parallel to each other and are located at different level heights.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 29, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Tung-Ying Lee, Da-Ching Chiou
  • Publication number: 20250176443
    Abstract: A memory device includes a memory cell, a protection coating, and a first sidewall spacer. The memory cell is disposed over an inter-metal dielectric (IMD) layer. The memory cell includes a bottom electrode, a top electrode and a resistance-switchable structure between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the resistance-switchable structure. The protection coating consists of a binary compound of carbon and hydrogen. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.
    Type: Application
    Filed: January 28, 2025
    Publication date: May 29, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chao LIN, Yuan-Tien TU, Shao-Ming YU, Tung-Ying LEE
  • Publication number: 20250176240
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 29, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Tai CHANG, Tung-Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
  • Patent number: 12317529
    Abstract: A device includes a plurality of semiconductor fins extending from a substrate. A plurality of first source/drain regions are epitaxially grown from first regions of the semiconductor fins. Adjacent two of the plurality of first source/drain regions grown from adjacent two of the plurality of semiconductor fins are spaced apart by an isolation dielectric. A gate structure laterally surrounds second regions of the plurality of semiconductor fins above the first regions of the plurality of semiconductor fins. A plurality of second source/drain regions are over third regions of the plurality of semiconductor fins above the second regions of the plurality of semiconductor fins.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Tung-Ying Lee, Chih-Chieh Yeh
  • Patent number: 12317515
    Abstract: A memory device and a semiconductor die are provided. The memory device includes single-level-cells (SLCs) and multi-level-cells (MLCs). Each of the SLCs and the MLCs includes: a phase change layer; and a first electrode, in contact with the phase change layer, and configured to provide joule heat to the phase change layer during a programming operation. The first electrode in each of the MLCs is greater in footprint area as compared to the first electrode in each of the SLCs.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Win-San Khwa, Yu-Chao Lin, Chien-Hsing Lee
  • Patent number: 12317761
    Abstract: A phase-change memory device and a method for fabricating the same are provided. The phase-change memory device comprises a first electrode, a stack and a multi-layered spacer. The first electrode is disposed on and electrically connected to an interconnect wiring of the interconnect structure. The stack is disposed on the first electrode and comprises a phase-change layer disposed on the first electrode and a second electrode disposed on the phase-change layer. The multi-layered spacer covers the stack. A first portion of the multi-layered spacer covers a top surface of the stack, and a second portion of the multi-layered spacer covers a sidewall of the stack.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Yu-Chao Lin, Tung-Ying Lee
  • Patent number: 12302765
    Abstract: A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.
    Type: Grant
    Filed: February 20, 2024
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Feng Hsu, Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Hengyuan Lee, Xinyu Bao
  • Publication number: 20250142919
    Abstract: A semiconductor device includes a channel structure, source region, a drain region, metal gate structure, and a self-assembled layer. The source region and the drain region are on opposite sides of the channel structure. A bottom surface of the source region is lower than a bottom surface of the channel structure, and a top surface of the source region is higher than a top surface of the channel structure. The metal gate structure covers the channel structure and between the source region and the drain region. The self-assembled layer is between the source region and the metal gate structure. The self-assembled layer is in contact with the bottom surface of the channel structure but spaced apart from the top surface of the channel structure.
    Type: Application
    Filed: January 3, 2025
    Publication date: May 1, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Tung-Ying LEE, Tse-An CHEN, Tzu-Chung WANG, Miin-Jang CHEN, Yu-Tung YIN, Meng-Chien YANG
  • Publication number: 20250126842
    Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 17, 2025
    Inventors: Tung Ying Lee, Kai-Tai Chang, Meng-Hsuan Hsiao
  • Publication number: 20250126881
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first active region and a second active region adjacent to the first active region, a first gate stack extending across the first active region in a first direction, an isolation feature extending across the second active region in the first direction; and a first gate-cut feature sandwiched between the first gate stack and the isolation feature.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun NG, Yu-Chao LIN, Tung-Ying LEE