Patents by Inventor Tung-Ying Lee

Tung-Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240074334
    Abstract: A phase-change memory device and a method for fabricating the same are provided. The phase-change memory device comprises a first electrode, a stack and a multi-layered spacer. The first electrode is disposed on and electrically connected to an interconnect wiring of the interconnect structure. The stack is disposed on the first electrode and comprises a phase-change layer disposed on the first electrode and a second electrode disposed on the phase-change layer. The multi-layered spacer covers the stack. A first portion of the multi-layered spacer covers a top surface of the stack, and a second portion of the multi-layered spacer covers a sidewall of the stack.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Yu-Chao Lin, Tung-Ying Lee
  • Patent number: 11901452
    Abstract: A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Winnie Chen
  • Publication number: 20240049477
    Abstract: A memory device and a semiconductor die are provided. The memory device includes single-level-cells (SLCs) and multi-level-cells (MLCs). Each of the SLCs and the MLCs includes: a phase change layer; and a first electrode, in contact with the phase change layer, and configured to provide joule heat to the phase change layer during a programming operation. The first electrode in each of the MLCs is greater in footprint area as compared to the first electrode in each of the SLCs.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Win-San Khwa, Yu-Chao Lin, Chien-Hsing Lee
  • Patent number: 11891623
    Abstract: Provided herein are isolated neural stem cells and methods of making neural stem cells from human trophoblast stem cells. The isolated neural stem cells can be immune privileged and express one or more protein(s). Also provided are methods for treatment of neurodegenerative diseases using suitable preparations comprising the isolated neural stem cells.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: February 6, 2024
    Assignee: Accelerated BioSciences Corp.
    Inventors: Jau-Nan Lee, Tony Tung-Ying Lee, Yuta Lee, Eing-Mei Tsai
  • Publication number: 20240040938
    Abstract: A memory device includes a substrate, a first signal line, a first dielectric layer, a phase change layer, a second dielectric layer, a first electrode, a second electrode and a second signal line. The first signal line is disposed over the substrate. The first dielectric layer is disposed over the first signal line. The phase change layer is disposed over the first dielectric layer. The second dielectric layer is disposed over the phase change layer. The first electrode and the second electrode are penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is located between the first electrode and the second electrode. The second signal line is disposed over the second dielectric layer, wherein the first signal line is electrically connected with the first electrode, and the second signal line is electrically connected with the second electrode.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Jung-Piao Chiu, Shao-Ming Yu, Yuan-Tien Tu, Tung-Ying Lee
  • Publication number: 20240040802
    Abstract: A memory device includes a substrate, a bottom electrode disposed over the substrate, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer. The selector layer is an oxygen-doped chalcogenide based film, and an oxygen content of the selector layer is about 10 at % or less.
    Type: Application
    Filed: January 11, 2023
    Publication date: February 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Wu, Chen-Feng Hsu, Chien-Min Lee, Tung-Ying Lee, Xinyu BAO, Elia Ambrosi, Hengyuan Lee
  • Publication number: 20240023462
    Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating. The protection coating forms a first interface with the phase change element. The first interface has a first slope at a first position and a second slope at a second position higher than the first position, the second slope is different from the first slope.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chao LIN, Yuan-Tien TU, Shao-Ming YU, Tung-Ying LEE
  • Publication number: 20240021692
    Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.
    Type: Application
    Filed: August 2, 2023
    Publication date: January 18, 2024
    Inventors: Tung Ying Lee, Shao-Ming Yu, Tzu-Chung Wang
  • Publication number: 20240016070
    Abstract: A memory cell includes a bottom electrode, a first dielectric layer, a top electrode, and a variable resistance layer. The first dielectric layer laterally surrounds the bottom electrode. The top electrode is disposed over the bottom electrode and the first dielectric layer. The variable resistance layer is sandwiched between the bottom electrode and the top electrode and between the first dielectric layer and the top electrode. The variable resistance layer exhibits a T-shape in a cross-sectional view.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Tung-Ying Lee, Da-Ching Chiou
  • Publication number: 20240015988
    Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Xinyu BAO, Hengyuan Lee, Ying-Yu Chen
  • Publication number: 20240008375
    Abstract: A memory device and a fabrication method thereof are provided. The memory device includes a substrate, a seed layer over the substrate, a superlattice structure in contact with the seed layer and a top electrode over the superlattice structure. The seed layer comprises carbon and silicon. The superlattice structure comprises first metal layers and second metal layers stacked alternately.
    Type: Application
    Filed: July 3, 2022
    Publication date: January 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Tung-Ying Lee, Shao-Ming Yu
  • Patent number: 11864477
    Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. The storage element layer has a first inclined sidewall, the top electrode has a second inclined sidewall, and an angle of the first inclined sidewall is greater than an angle of the second inclined sidewall. A semiconductor device having the memory cell is also provided.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Tung-Ying Lee
  • Publication number: 20230420250
    Abstract: A method for manufacturing a semiconductor device includes the following steps. A transition metal layer is formed over a substrate in a reaction chamber; a chalcogen-containing fluid is flowed into the reaction chamber; and a heating process is performed in the reaction chamber over the transition metal layer with the chalcogen-containing fluid to transform the transition metal layer into a two-dimensional (2D) material layer over the substrate.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Yu-Chao Lin, Tung-Ying Lee
  • Patent number: 11856876
    Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • Publication number: 20230411215
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.
    Type: Application
    Filed: July 28, 2023
    Publication date: December 21, 2023
    Inventors: Shao-Ming YU, Tung Ying LEE, Wei-Sheng YUN, Fu-Hsiang YANG
  • Patent number: 11848365
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate structure wrapping around a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate structure. The semiconductor device structure includes a source/drain structure over the fin. The source/drain structure is over a side of the gate structure and connected to the first nanostructure, the source/drain structure has an upper portion, a lower portion, and a neck portion between the upper portion and the lower portion, the upper portion has a first diamond-like shape, and the lower portion is wider than the neck portion.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Kai-Tai Chang
  • Patent number: 11849655
    Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang
  • Publication number: 20230397439
    Abstract: Provided is a memory cell including a selector disposed over a substrate, a memory element and a connecting pad. The selector includes a bottom electrode, an ovonic threshold switch layer on the bottom electrode, an inter-electrode over the ovonic threshold switch layer, and an intermediate layer between the ovonic threshold switch layer and the inter-electrode. The memory element is disposed on the selector. The connecting pad is disposed on the memory element.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Tung-Ying Lee
  • Publication number: 20230389452
    Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • Publication number: 20230389440
    Abstract: A magnetic memory device includes a substrate, a spin-orbit torque (SOT) induction structure, and a magnetic tunnel junction (MTJ) stack. The SOT induction structure is disposed over the substrate. The SOT induction structure includes a metal and at least one dopant. The MTJ stack is disposed over the SOT induction structure.
    Type: Application
    Filed: September 1, 2022
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yuan Song, Chien-Min Lee, Shy-Jay Lin, Tung-Ying Lee, Xinyu BAO