Patents by Inventor Tung-Ying Lee

Tung-Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220255000
    Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. The storage element layer has a first inclined sidewall, the top electrode has a second inclined sidewall, and an angle of the first inclined sidewall is greater than an angle of the second inclined sidewall. A semiconductor device having the memory cell is also provided.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Tung-Ying Lee
  • Publication number: 20220254929
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and a sidewall of the first portion of the gate dielectric layer extends beyond a sidewall of the filling layer.
    Type: Application
    Filed: April 26, 2022
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao LIN, Wei-Sheng YUN, Tung-Ying LEE
  • Patent number: 11411083
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a first fin and a second fin formed over the substrate. The semiconductor structure further includes a first anti-punch through region formed in the first fin and a second anti-punch through region formed in the second fin and first nanostructures formed over the first fin and second nanostructures formed over the second fin. The semiconductor structure further includes a barrier layer formed over the second anti-punch through region and a first gate formed around the first nanostructures. The semiconductor structure further includes a second gate formed around the second nanostructures. In addition, an interface between the barrier layer and the second anti-punch through region is higher than an interface between the first anti-punch through region and the first gate.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsuan Hsiao, Winnie Victoria Wei-Ning Chen, Tung Ying Lee
  • Patent number: 11411181
    Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Yu Chao Lin
  • Patent number: 11411180
    Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Yu Chao Lin, Shao-Ming Yu
  • Patent number: 11404635
    Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.
    Type: Grant
    Filed: January 19, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • Publication number: 20220238523
    Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi PENG, Chun-Chieh LU, Meng-Hsuan HSIAO, Ling-Yen YEH, Carlos H. DIAZ, Tung-Ying LEE
  • Patent number: 11393925
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Yu-Chao Lin, Chao-Ching Cheng, Tzu-Chiang Chen, Tung-Ying Lee
  • Publication number: 20220223785
    Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.
    Type: Application
    Filed: July 7, 2021
    Publication date: July 14, 2022
    Inventors: Chien-Min Lee, Shy-Jay Lin, Yen-Lin Huang, MingYuan Song, Tung Ying Lee
  • Patent number: 11387102
    Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu
  • Patent number: 11387360
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
  • Publication number: 20220216403
    Abstract: A memory cell includes pair of metal layers, insulating layer, memory layer, selector layer, and word line. The pair of metal layers extends in a first direction. A first metal layer of the pair is disposed in contact with a second metal layer of the pair. The first metal layer includes a first material. The second metal layer includes a second material. The second metal layer laterally protrudes with respect to the first metal layer along a second direction perpendicular to the first direction. The insulating layer extends in the first direction and is disposed on top of the pair. The memory layer conformally covers sides of the pair. The selector layer is disposed on the memory layer. The word line extends along the second direction on the selector layer over the pair.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 7, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Tai Chang, Tung-Ying Lee
  • Patent number: 11380090
    Abstract: A method for object recognition at an interactive information system (IIS) includes capturing, using an imaging device of the IIS, a first image of a first representative object which represents a first one or more object disposed about the IIS; analyzing, by a computer processor of the IIS and based on a category model, the first image to determine a first representative category of the first one or more object; retrieving, by the computer processor and based on the first representative category, a first representative object model of a plurality of object models that are stored on a remote server; and analyzing, by the computer processor and based on the first representative object model, the first image to determine a first representative inventory identifier of the first representative object, which represents a first one or more inventory identifier corresponding to the first one or more object respectively.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 5, 2022
    Assignee: Flytech Technology Co., Ltd.
    Inventors: Tung-Ying Lee, Yi-Heng Tseng, Tzu-Wei Huang, Che-Wei Lin
  • Publication number: 20220209106
    Abstract: A phase change memory device includes a bottom conductive line, a dielectric layer, a bottom memory layer, and a top electrode. The dielectric layer covers the bottom conductive line. The bottom memory layer is in the dielectric layer and is electrically connected to the bottom conductive line. The bottom memory layer includes a tapered portion and a neck portion. The tapered portion is over the bottom conductive line and is tapered toward the bottom conductive line. The neck portion is directly between the tapered portion and the bottom conductive line. The neck portion has a substantially constant width. The top electrode is over and electrically connected to the bottom memory layer.
    Type: Application
    Filed: March 15, 2022
    Publication date: June 30, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Ying LEE, Shao-Ming YU, Yu-Chao LIN
  • Patent number: 11362277
    Abstract: A method of forming a phase change random access memory (PCRAM) device includes forming a phase change element over a bottom electrode and a top electrode over the phase change element, forming a protection layer around the phase change element, and forming a nitrogen-containing sidewall spacer layer around the protection layer after forming the protection layer.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chao Lin, Yuan-Tien Tu, Shao-Ming Yu, Tung-Ying Lee
  • Patent number: 11355605
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, and a second nanostructure. The method includes forming an isolation layer over the base. The method includes forming a gate dielectric layer over the first nanostructure, the second nanostructure, the fin, and the isolation layer. The method includes forming a gate electrode layer over the first part. The method includes forming a spacer layer. The method includes removing the second part of the gate dielectric layer and the first upper portion of the isolation layer to form a space between the fin and the spacer layer. The method includes forming a source/drain structure in the space and over the first nanostructure and the second nanostructure.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Kai-Tai Chang
  • Patent number: 11342501
    Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, a storage element layer, and a protective layer. The storage element layer is disposed between the bottom and top electrodes. The protective layer covers the storage element layer and the top electrode, and a material of the protective layer is derived from the storage element layer. A semiconductor device having the memory cell is also provided.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Tung-Ying Lee
  • Publication number: 20220157665
    Abstract: A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.
    Type: Application
    Filed: February 3, 2022
    Publication date: May 19, 2022
    Inventors: Tzu-Chung WANG, Tung Ying LEE
  • Publication number: 20220149274
    Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Carlos H. Diaz, Shao-Ming Yu, Tung-Ying Lee
  • Publication number: 20220149177
    Abstract: A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 12, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Tung-Ying LEE, Tse-An CHEN, Tzu-Chung WANG, Miin-Jang CHEN, Yu-Tung YIN, Meng-Chien YANG