Abstract: A local interconnect fabrication method is disclosed. A nitride spacer is formed on each sidewall of an etched recess formed across a shallow trench isolation region. The spacer prevents contact of metal with the exposed silicon substrate in the recess, and thus reduces leakage. High performance and low energy dissipation of devices can be achieved by reducing undesirable leakage current.

Abstract: The present invention provides a method of forming a doped region with a DDD on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a pad oxide layer, and a silicon nitride layer that is used to define an active area. A lithographic process is performed to define a position of the DDD. Then a first ion implantation process is performed to implant a specific dosage of dopants into the silicon substrate. The photoresist layer is then removed completely. A thermal oxidation process is performed to form a field oxide layer in the region not covered by the silicon nitride layer, and to simultaneously drive the dopants into the silicon substrate so as to form a doped region. The silicon nitride layer and the pad oxide layer are removed. Then a poly gate and a spacer are formed. A second ion implantation process is performed to implant ions into the silicon substrate so as to form the doped region with a DDD structure in the N-type MOS transistor.

Abstract: A method for integrating a high-voltage device and a low-voltage device. A substrate has a high-voltage device region, a low-voltage device region and a scribe region, wherein a patterned insulating layer is formed on the substrate in the high-voltage device region and the scribe region. A grade region is formed in the substrate exposed by the patterned insulating layer in the high-voltage device region. A plurality of protuberances is formed on the substrate exposed by the patterned insulating layer in the high-voltage device region and in the scribe region. The patterned insulating layer and the protuberances are removed to form recesses at locations of the protuberances. A first gate structure and a second gate structure are respectively formed on the substrate between the grade region in the high-voltage device region and on the substrate in the low-voltage device region while using the recesses as alignment marks.