Patents by Inventor Tuo-Hung Ho

Tuo-Hung Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250103751
    Abstract: A computing circuit with a de-identified architecture, a data computing method, a data processing system, and a data de-identification method are provided. The computing circuit includes an arithmetic array and a de-identification circuit. The computing circuit may perform an accumulation operation on input data to generate accumulated data by the arithmetic array. The de-identification circuit has an analog offset error determined based on an analog physical unclonable function. The computing circuit may operate the accumulated data according to the analog offset error to generate de-identification data by the de-identification circuit. It can not only provide the analog offset error through the transistors in the de-identification circuit, but also be combined with obfuscated code settings to dynamically adjusting the degree of de-identification of data.
    Type: Application
    Filed: September 26, 2024
    Publication date: March 27, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Bo-Cheng Chiou, Chih-Sheng Lin, Tuo-Hung Hou, Chih-Ming Lai, Yun-Ting Ho, Shan-Ming Chang
  • Patent number: 7271450
    Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: September 18, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tuo-Hung Ho, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao, Chih-Chang Chen
  • Publication number: 20060091469
    Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
    Type: Application
    Filed: December 16, 2005
    Publication date: May 4, 2006
    Inventors: Tuo-Hung Ho, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao, Chih-Chang Chen
  • Patent number: 7030024
    Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: April 18, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tuo-Hung Ho, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao, Chih-Chang Chen
  • Patent number: 6764927
    Abstract: A chemical vapor deposition (CVD) method for forming a microelectronic layer within a microelectronic product employs a wetting material treatment of a substrate upon which is formed the microelectronic layer. The wetting material treatment provides for an attenuated incubation or induction time when forming the microelectronic layer, particularly within the context of a digital CVD method, such as an atomic layer CVD method. The microelectronic layer is thus formed with enhanced manufacturability.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: July 20, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Liang-Gi Yao, Ming-Fang Wang, Yeou-Ming Lin, Tuo-Hung Ho, Shih-Chang Chen
  • Publication number: 20040038538
    Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 26, 2004
    Inventors: Tuo-Hung Ho, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao, Chih-Chang Chen