Patents by Inventor Tuo Li

Tuo Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967698
    Abstract: Provided are a rolling apparatus and a processing device, which are used for rolling an electrode plate. The rolling apparatus includes a first roller and a second roller, where the first roller and the second roller are disposed at two sides of the electrode plate in a thickness direction of the electrode plate. The first roller is provided with a plurality of recessed portions, the electrode plate includes a plurality of insulation coating layer regions and a plurality of tabs, and in a projection of the electrode plate in the thickness direction, at least part of a projection of the insulation coating layer region and a projection of the tab are located within a projection of the recessed portion. The rollers deflect under a large rolling pressure.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: April 23, 2024
    Assignee: JIANGSU CONTEMPORARY AMPEREX TECHNOLOGY LIMITED
    Inventors: Zhikai Deng, Shisong Li, Tuo Zheng, Xuanyin Chen
  • Patent number: 11933924
    Abstract: The present disclosure provides an active pixel sensor and a flat panel detector. The active pixel sensor includes: a light sensing device configured to convert light sensed by the light sensing device into charges and supply the charges to a floating diffusion node; an amplification sub-circuit configured to amplify a signal according to a potential at the floating diffusion node and output the amplified signal through the output terminal; an adjustment sub-circuit configured to adjust, in response to a first control signal, a conversion gain from an amount of the light sensed by the light sensing device to the potential at the floating diffusion node; and a read sub-circuit configured to transmit a voltage of the input terminal of the read sub-circuit to the output terminal of the read sub-circuit according to a scan signal provided by the scan line.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: March 19, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiangbo Chen, Fanli Meng, Zeyuan Li, Yao Lu, Tuo Sun, Yanzhao Li, Ding Ding
  • Patent number: 11937427
    Abstract: In certain aspects, a first opening extending vertically through a first dielectric deck including a first plurality of interleaved sacrificial layers and dielectric layers above a substrate is formed. A high-k dielectric layer and a channel sacrificial layer free of polysilicon are subsequently formed along a sidewall of the first opening. A second opening extending vertically through a second dielectric deck including a second plurality of interleaved sacrificial layers and dielectric layers on the first dielectric deck is formed to expose the channel sacrificial layer in the first opening. The channel sacrificial layer is removed in the first opening. A memory film and a semiconductor channel are subsequently formed over the high-k dielectric layer along sidewalls of the first and second openings.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: March 19, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Shuangshuang Peng, Jingjing Geng, Jiajia Wu, Tuo Li
  • Publication number: 20240088246
    Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
  • Patent number: 11908689
    Abstract: The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a Nb2N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb2N sacrificial layer; growing a Ta2N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta2N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb2N sacrificial layer and the Ta2N sacrificial layer; and transferring remaining material after removal of the Nb2N sacrificial layer and the Ta2N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 20, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Fen Guo, Kang Su, Lang Zhou, Tuo Li, Hongtao Man
  • Publication number: 20230395375
    Abstract: The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a Nb2N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb2N sacrificial layer; growing a Ta2N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta2N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb2N sacrificial layer and the Ta2N sacrificial layer; and transferring remaining material after removal of the Nb2N sacrificial layer and the Ta2N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.
    Type: Application
    Filed: October 29, 2021
    Publication date: December 7, 2023
    Inventors: Fen GUO, Kang SU, Lang ZHOU, Tuo LI, Hongtao MAN
  • Patent number: 11800707
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a channel structure extending vertically through the memory stack. The channel structure includes a high dielectric constant (high-k) dielectric layer disposed continuously along a sidewall of the channel structure, a memory film over the high-k dielectric layer along the sidewall of the channel structure, and a semiconductor channel over the memory film along the sidewall of the channel structure.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 24, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Shuangshuang Peng, Jingjing Geng, Jiajia Wu, Tuo Li
  • Publication number: 20230134694
    Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a layer stack, a channel hole, a blocking layer, a charge trap layer, a tunnel insulation layer, and a channel layer. The surface region of the charge trap layer includes a carbon region that contains a certain amount of carbon elements.
    Type: Application
    Filed: December 6, 2021
    Publication date: May 4, 2023
    Inventors: Qiguang WANG, Hao PU, Tuo LI, Yingjie ZHAO
  • Publication number: 20230049578
    Abstract: The method comprises: connecting to a plurality of AI computing boards in an AI processing resource pool and a plurality of video encoding and decoding boards in a video processing resource pool by means of a unified high-speed interface; respectively allocating a specified number of AI computing boards and video encoding and decoding boards on account of resources and bandwidths required for completing a processing task to form a temporary cooperation relationship based on the processing task; in response to resource overflow or insufficiency in the AI processing resource pool or the video processing resource pool caused by a processing task change, accessing more AI computing boards or video encoding and decoding boards or stopping using redundant AI computing boards or video encoding and decoding boards; performing the processing task on account of the allocated AI computing boards or video encoding and decoding boards, and releasing the temporary cooperation relationship.
    Type: Application
    Filed: August 26, 2020
    Publication date: February 16, 2023
    Inventor: Tuo LI
  • Publication number: 20220398495
    Abstract: A data analytics platform may be configured to construct an inferential model for a multivariate observation vector using inferential modeling in combination with component analysis, which may enable the data analytics platform evaluate only a subset of the variables in the observation vector and then output a predicted version of the multivariate observation vector that includes predicted values for the full set of variables that was originally included in the observation vector. In turn, the data analytics platform may use the predicted version of the multivariate observation vector output by the inferential model to determine whether an anomaly has occurred.
    Type: Application
    Filed: January 24, 2022
    Publication date: December 15, 2022
    Inventors: Tuo Li, James Herzog
  • Publication number: 20220310643
    Abstract: Semiconductor fabrication methods and semiconductor devices are disclosed. According to some aspects, a memory device includes a memory stack having interleaved a plurality of conductive layers and a plurality of insulating layers on a substrate, and a channel structure extending vertically in the memory stack. The channel structure includes a semiconductor channel extending vertically in the memory stack and conductively connected to a source structure. The semiconductor channel includes polysilicon, and a grain size of the polysilicon ranges from 100 nm to 600 nm.
    Type: Application
    Filed: June 18, 2021
    Publication date: September 29, 2022
    Inventors: Tuo Li, Hao Pu, Lei Li, Caiyu Wu
  • Publication number: 20220236992
    Abstract: A RISC-V branch prediction method and device, an electronic device and a computer readable storage medium are provided. On the basis of the prior art, the remaining jump times of the jump instruction are additionally acquired, and the single jump step length (the single jump step length is not fixed to be 1) is calculated according to the difference of remaining jump times during two consecutive jumps, whether the target jump instruction has executed the last jump can be judged according to the single jump step length of a jump instruction and in combination with the real-time remaining jump times, so as to determine the jump times that need to be executed subsequently according to the judgment result.
    Type: Application
    Filed: August 30, 2019
    Publication date: July 28, 2022
    Inventors: Tongqiang Liu, Chaohui Wang, Rengang Li, Tuo Li, Yulong Zhou, Xiaofeng Zou
  • Patent number: 11232371
    Abstract: A data analytics platform may be configured to construct an inferential model for a multivariate observation vector using inferential modeling in combination with component analysis, which may enable the data analytics platform to evaluate only a subset of the variables in the observation vector and then output a predicted version of the multivariate observation vector that includes predicted values for the full set of variables that was originally included in the observation vector. In turn, the data analytics platform may use the predicted version of the multivariate observation vector output by the inferential model to determine whether an anomaly has occurred.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: January 25, 2022
    Assignee: Uptake Technologies, Inc.
    Inventors: Tuo Li, James Herzog
  • Publication number: 20210305274
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a channel structure extending vertically through the memory stack. The channel structure includes a high dielectric constant (high-k) dielectric layer disposed continuously along a sidewall of the channel structure, a memory film over the high-k dielectric layer along the sidewall of the channel structure, and a semiconductor channel over the memory film along the sidewall of the channel structure.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 30, 2021
    Inventors: Shuangshuang Peng, Jingjing Geng, Jiajia Wu, Tuo Li
  • Publication number: 20210305277
    Abstract: In certain aspects, a first opening extending vertically through a first dielectric deck including a first plurality of interleaved sacrificial layers and dielectric layers above a substrate is formed. A high-k dielectric layer and a channel sacrificial layer free of polysilicon are subsequently formed along a sidewall of the first opening. A second opening extending vertically through a second dielectric deck including a second plurality of interleaved sacrificial layers and dielectric layers on the first dielectric deck is formed to expose the channel sacrificial layer in the first opening. The channel sacrificial layer is removed in the first opening. A memory film and a semiconductor channel are subsequently formed over the high-k dielectric layer along sidewalls of the first and second openings.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 30, 2021
    Inventors: Shuangshuang Peng, Jingjing Geng, Jiajia Wu, Tuo Li
  • Patent number: 10635095
    Abstract: The example systems, methods, and devices disclosed herein generally relate to generating create a supervised failure model for assets in the given fleet that is configured to receive operating data as inputs and output a prediction as to the occurrence of a given failure type at the asset. In some instances, a data analytics platform may create and use an unsupervised failure model for a subset of the assets, use the respective unsupervised failure models to detect a set of anomalies that are each suggestive of a prior failure occurrence, from the set of anomalies, identify a subset of anomalies that are each suggest of a prior failure occurrence of the given failure type, and create the supervised failure model using failure data for the identified subset of anomalies.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 28, 2020
    Assignee: Uptake Technologies, Inc.
    Inventors: James Herzog, Benedict Augustine, Brian Burns, Eric Hall, Tuo Li
  • Patent number: 10635519
    Abstract: A computing platform may obtain observed data vectors related to the operation of a topology of nodes that represents a software application running on an uncontrolled platform, wherein each observed data vector comprises data values captured for a given set of operating variables at a particular point in time. After obtaining the observed data vectors, the computing platform may apply an anomaly detection model to the observed data vectors and then based on the anomaly detection model, may identify an anomaly in at least one operating variable. In turn, the computing platform may determine whether each identified anomaly is indicative of a problem related to the application, and based on a determination that an identified anomaly is indicative of a problem related to the software application, cause a client station to present a notification.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 28, 2020
    Assignee: Uptake Technologies, Inc.
    Inventors: Yuan Tang, Tuo Li, James Herzog
  • Patent number: 10541903
    Abstract: A system and method of improving anomaly detection rate in a communication network. A server computer may receive a data set comprising traffic flows communicated over the communication network and group the traffic flows into data categories based on the type of network service such as transport control protocol (TCP) port numbers or User Datagram Protocol (UDP) port numbers of the traffic flows, or based on application layer protocols associated with the traffic flows. The server computer may further detect anomalies in each of the data categories based on inconsistencies between at least one common feature associated with a data category and traffic flows in the data category. Different data categories may be associated with different the at least one common feature. The anomaly detection may be supervised or unsupervised.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: January 21, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Zhibi Wang, Tuo Li
  • Patent number: 10474932
    Abstract: Disclosed herein are systems, devices, and methods for detecting anomalies in multivariate data received from an asset-related data source, such as signal data and/or other data from an asset. According to an example, a platform may receive multivariate data from an asset in an original coordinate space and transform the data in the original coordinate space to a transformed coordinate space having a relatively fewer number of dimensions. Additionally, the platform may standardize the data in the transformed coordinate space and modify the standardized data based on a comparison between the standardized data and a set of threshold values previously defined via training data reflective of normal asset operation. Thereafter, the platform may inversely transform the modified data back to the original coordinate space and perform an analysis to detect anomalies.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: November 12, 2019
    Assignee: Uptake Technologies, Inc.
    Inventors: Frank Fineis, Michael Horrell, Tuo Li, James Herzog
  • Publication number: 20190324430
    Abstract: The example systems, methods, and devices disclosed herein generally relate to generating create a supervised failure model for assets in the given fleet that is configured to receive operating data as inputs and output a prediction as to the occurrence of a given failure type at the asset. In some instances, a data analytics platform may create and use an unsupervised failure model for a subset of the assets, use the respective unsupervised failure models to detect a set of anomalies that are each suggestive of a prior failure occurrence, from the set of anomalies, identify a subset of anomalies that are each suggest of a prior failure occurrence of the given failure type, and create the supervised failure model using failure data for the identified subset of anomalies.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 24, 2019
    Inventors: James Herzog, Benedict Augustine, Brian Burns, Eric Hall, Tuo Li