Abstract: The present application relates to a dynamic self-adaptive virtual channel mapping method and apparatus, and a storage medium. The method includes: monitoring equivalent data flows of transaction layer packets of different transmit classes, and obtaining the sum of the equivalent data flows of all the transmit classes, the equivalent data flow being the product of a data length of the transaction layer packet and a coefficient; obtaining a pre-calculation value of the number of virtual channels corresponding to each transmit class base on the sum of the equivalent data flows of the transmit classes; and adjusting mapping from the transmit classes to the virtual channels according to the pre-calculation value to obtain a mapping relationship table from the transmit classes to the virtual channels.

Abstract: In some embodiments, a method receives a first instance of data for anomaly detection. The first instance of data includes values from multiple variables. The first instance of data is stored in a queue. The method weights instances of data in the queue based on data changing over time and projects the instances of the data in the queue into a space. A point in the space represents a correlation of the values for the multiple variables for a respective instance of data. A boundary is generated based on the points in the space. Then, the method determines a point in the space that is considered an anomaly based on the boundary.

Abstract: The present application discloses an interconnect apparatus for a bus, including at least one decoder, configured to determine, according to at least one read instruction sent by at least one master device, at least one slave device corresponding to the at least one read instruction; a read instruction ID state recording component, Configured to determine the slave device corresponding to the read instruction in response to the decoder, and query, on the basis of a second port of the memory, whether an interconnect apparatus contains a read instruction having the same ID as that of a current read instruction, and configured to route, on the basis of a query result, the current read instruction to a slave device buffer component or a same-ID sorting buffer component corresponding to the read instruction, and write a value into the memory on the basis of a first port of the memory.

Abstract: The present application discloses method for transmitting video data, applied to chip for substrate management control. The method includes: respectively storing video compression data into first storage space and second storage space according to ping-pong operation structure; reading data of the same byte length from the first storage space and the second storage space; determining whether similarity between first data to be transmitted and second data to be transmitted is greater than or equal to preset value; if yes, setting the first data to be transmitted added with first transmission identifier as the current frame of data, and setting a second transmission identifier corresponding to the first transmission identifier as the next frame of data; and sending the current frame data and the next frame data to video data receiving end.

Abstract: The present application discloses a branch instruction processing method, system, and device, and a computer storage medium. The method includes: determining, on the basis of a target branch instruction, a branch instruction to be predicted (S101); predicting, on the basis of a plurality of preset branch prediction methods, the branch instruction to be predicted, so as to obtain a corresponding prediction result (S102); determining the prediction accuracy of each branch prediction method on the basis of the prediction result (S103); determining the branch prediction method corresponding to the highest prediction accuracy as a target branch prediction method (S104); and performing branch prediction on the target branch instruction on the basis of the target branch prediction method (S105).

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Some implementations described herein include a semiconductor device including a semiconductor resistor structure having and techniques for forming the semiconductor resistor structure. The techniques include forming a layer of a silicon chromium material having different silicon/chromium ratios within the layer (e.g., a graded resistive layer) as part of forming the semiconductor resistor structure. The graded resistive layer may compensate for semiconductor manufacturing processes (e.g., etching, oxidation, thermal annealing) that may lead to film damage, thinning, crystallization, or composition drift of the graded resistive layer to enlarge process windows for fabricating the semiconductor resistor structure. The enlarged process window may improve a performance of the semiconductor resistor structure (e.g., a resistance and/or an impedance uniformity) relative to another semiconductor resistor structure fabricated using a uniform layer of a silicon chromium material.

Abstract: A method for preparing a sensing device is provided, the method includes: forming, on a surface of a transparent substrate, a first auxiliary patterning layer having a trench; and forming a mesh structure in the trench of the first auxiliary patterning layer by means of an electroplating process, or forming a conductive layer in the trench of the first auxiliary patterning layer by means of an electroplating process and then etching the conductive layer to form a mesh structure. The mesh structure has a line width of less than or equal to 1.5 microns and a thickness of greater than or equal to 2 microns.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: The present invention relates to the field of genetic engineering and process engineering, and discloses an engineering strain producing cordycepin and its derivative 3?-deoxyinosine, its preparation method and application. The method includes: codon optimizing genes Cm1 and Cm2; gene amplification and fragment recovering; methanol-induced promoter and terminator fragments; and inserting the genes into an expression vector and then transferring to Pichia pastoris for screening to obtain the engineering strain of Pichia pastoris of the present invention. The engineering strain can be applied to production of cordycepin and its derivative. The engineering strain prepared by the preparation method of the present invention has great advantages in producing cordycepin and its derivative.

Abstract: A pixel driving circuit is provided. The pixel driving circuit includes a light emission control circuit and a drive circuit. The light emission control circuit controls a potential of a control terminal of the drive circuit under the control of a coupled signal terminal, and the drive circuit drives a coupled light-emitting element to emit light based on the potential of the control terminal thereof. The drive circuit includes two drive transistors connected in parallel, and subthreshold swings of the two drive transistors are different.

Abstract: An electronic device and a memristor-based logic gate circuit thereof. In the present application, a control end of a controllable switch is connected to a negative end of an output memristor in a MAGIC-based AND logic gate, and whether a second memristor is powered on is controlled by the controllable switch. Thus, when resistance value states of two input memristors in the AND logic gate are different, the controllable switch will conduct and power on the second memristor, and the second memristor will present a low-resistance state at this time. When the resistance value states of the two input memristors are the same, the controllable switch will not conduct and the second memristor will then remain the state unchanged, i.e., presents a high-resistance state. An exclusive OR logic gate is formed by combining the two input memristors and the second memristor.

Abstract: Disclosed is a method for stripping a gallium nitride substrate, including: a gallium nitride substrate with a gallium nitride epitaxial structure directly grown on an upper surface thereof is acquired; an interior of the gallium nitride substrate is scanned and irradiated via the epitaxial structure by a laser beam, so as to generate a decomposition layer in the gallium nitride substrate, the laser beam being a laser having a pulse width on the order of less than 10?15 s, and a distance between the decomposition layer and the upper surface of the gallium nitride substrate being less than a thickness of the gallium nitride substrate; and the gallium nitride substrate is separated at the decomposition layer, so as to obtain a stripped gallium nitride substrate and a semiconductor device.

Abstract: An embodiment of the present application provide an electrode assembly, a battery cell, a battery, and an electrode assembly manufacturing equipment and method. Among that, the electrode assembly includes a negative electrode plate and a positive electrode plate which form a bending region. The positive electrode plate includes bending portions located in the bending region, the bending portion includes a positive electrode current collecting layer and a positive active substance layer, and at least one side surface of the positive electrode current collecting layer is provided with the positive active substance layer in a thickness direction of the positive electrode plate. At least one positive active substance layer is provided with the barrier layer, at least a part of the barrier layer is intercalated in the positive active substance layer provided with the barrier layer, and coats at least a part of particles in the positive active substance layer.

Abstract: Disclosed are an image output method and apparatus, and a computer-readable storage medium. The method includes: acquiring an image continuous change feature of a display interface of a local server; generating image output control information according to the image continuous change feature and a preset image change threshold; and controlling amount of output image data according to the image output control information and network congestion information.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Provided are a data processing method and apparatus for image compression, a device, and a storage medium. The method comprises: segmenting an image to be compressed into a plurality of image matrices, and performing first matrix calculation on elements of the image matrices to obtain first intermediate matrices; configuring a storage space size and storage addresses of the first intermediate matrices according to the resolution and pixel component depth of the image to be compressed performing second matrix calculation on elements of the first intermediate matrices and elements of a preset conversion matrix to obtain second intermediate matrices, and performing third matrix calculation on elements of the second intermediate matrices and the elements of the conversion matrix to obtain third intermediate matrices; and performing fourth matrix calculation on the conversion matrix and the third intermediate matrices to obtain result matrices, and encoding the result matrices to obtain a compressed image.

Abstract: An electronic device includes a main support, a first steel sheet, a camera assembly, and a fixation assembly, where the main support is provided with a mounting space, with a first face and a second face that are opposite each other. The first steel sheet is mounted to the first face of the main support and provided with a mounting portion located inside the mounting space. The camera assembly is mounted in the mounting portion, and a fixation assembly is mounted to the second face of the main support to fix the camera assembly in the mounting portion, where a gap is left between the mounting portion and the first face of the main support. The disclosed electronic device can increase space of a downside region of a mainboard, so as to satisfy the need of mounting of components.

Abstract: A monitoring video compression method, a monitoring system, a computer device, and a medium. The method includes: a monitoring center configuring a key monitoring point and sending configuration information of the key monitoring point to a video server through a management center; the video server receiving the configuration information of the key monitoring point, selecting a corresponding video source based on the configuration information of the key monitoring point, transferring the corresponding video source from a video compression module to a baseboard management controller (BMC) for compression, and writing the corresponding video source into a storage space of the video server after the compression is completed.

Abstract: Disclosed are a method and apparatus for processing video compression. The method includes: controlling a comparison apparatus to perform frame-wise writing of original video data to an external storage apparatus, and controlling a video compression control component to perform frame-wise reading of the original video data from the external storage apparatus; in response to writing original video data of a non-first frame into the external storage apparatus, and if yes, and in response to writing the original video data of the current frame into the external storage apparatus, converting the video data into tag information and writing the tag information into the external storage apparatus; and in response to reading the original video data of the previous frame from the external storage apparatus, writing the video data corresponding to the current same line number into an internal storage apparatus.