Patents by Inventor Tuoh-Bin Ng
Tuoh-Bin Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021466Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.Type: ApplicationFiled: August 8, 2023Publication date: January 18, 2024Inventors: Tzu-Ching Lin, Tuoh Bin Ng
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Patent number: 11823949Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.Type: GrantFiled: May 10, 2021Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Ching Lin, Tuoh Bin Ng
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Publication number: 20230360974Abstract: A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.Type: ApplicationFiled: July 19, 2023Publication date: November 9, 2023Inventors: Tzu-Ching Lin, Tuoh Bin Ng
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Patent number: 11749567Abstract: A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.Type: GrantFiled: July 19, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Tzu-Ching Lin, Tuoh Bin Ng
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Publication number: 20210351083Abstract: A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.Type: ApplicationFiled: July 19, 2021Publication date: November 11, 2021Inventors: Tzu-Ching Lin, Tuoh Bin Ng
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Publication number: 20210265196Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Tzu-Ching Lin, Tuoh Bin Ng
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Patent number: 11069578Abstract: A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.Type: GrantFiled: May 31, 2019Date of Patent: July 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Ching Lin, Tuoh Bin Ng
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Patent number: 11004725Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.Type: GrantFiled: June 14, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Ching Lin, Tuoh Bin Ng
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Patent number: 10991630Abstract: In an embodiment, a method includes: forming a first gate stack and a second gate stack on a fin; etching the fin to form a recess in the fin between the first gate stack and the second gate stack; forming an epitaxial source/drain region in the recess, the forming including: forming a first layer lining sides and a bottom of the recess by dispensing silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess; and after forming the first layer, forming a second layer on the first layer by dispensing the silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess, where each of the silane, dichlorosilane, trichlorosilane, and hydrochloric acid are dispensed at a first flow rate when forming the first layer and at a second flow rate when forming the second layer.Type: GrantFiled: July 30, 2019Date of Patent: April 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Ching Lin, Chien-Chih Lin, Feng-Ching Chu, Tuoh Bin Ng
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Publication number: 20200395237Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.Type: ApplicationFiled: June 14, 2019Publication date: December 17, 2020Inventors: Tzu-Ching Lin, Tuoh Bin Ng
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Publication number: 20200381309Abstract: A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.Type: ApplicationFiled: May 31, 2019Publication date: December 3, 2020Inventors: Tzu-Ching Lin, Tuoh Bin Ng
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Publication number: 20200105621Abstract: In an embodiment, a method includes: forming a first gate stack and a second gate stack on a fin; etching the fin to form a recess in the fin between the first gate stack and the second gate stack; forming an epitaxial source/drain region in the recess, the forming including: forming a first layer lining sides and a bottom of the recess by dispensing silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess; and after forming the first layer, forming a second layer on the first layer by dispensing the silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess, where each of the silane, dichlorosilane, trichlorosilane, and hydrochloric acid are dispensed at a first flow rate when forming the first layer and at a second flow rate when forming the second layer.Type: ApplicationFiled: July 30, 2019Publication date: April 2, 2020Inventors: Tzu-Ching Lin, Chien-Chih Lin, Feng-Ching Chu, Tuoh Bin Ng
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Patent number: 10340190Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation.Type: GrantFiled: November 24, 2017Date of Patent: July 2, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hao Lu, Yi-Fang Pai, Tuoh-Bin Ng, Li-Li Su, Chii-Horng Li
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Publication number: 20190164835Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation.Type: ApplicationFiled: November 24, 2017Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hao LU, Yi-Fang PAI, Tuoh-Bin NG, Li-Li SU, Chii-Horng LI
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Patent number: 10170370Abstract: A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.Type: GrantFiled: April 23, 2018Date of Patent: January 1, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wen Cheng, Chii-Horng Li, Lilly Su, Tuoh Bin Ng
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Publication number: 20180315660Abstract: A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.Type: ApplicationFiled: April 23, 2018Publication date: November 1, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wen CHENG, Chii-Horng Li, Lilly Su, Tuoh Bin Ng
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Patent number: 9953875Abstract: A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.Type: GrantFiled: April 21, 2017Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Cheng-Wen Cheng, Chii-Horng Li, Lilly Su, Tuoh Bin Ng
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Patent number: 9303318Abstract: In one embodiment, an apparatus includes a first gas distribution assembly that includes a first gas passage for introducing a first process gas into a second gas passage that introduces the first process gas into a processing chamber and a second gas distribution assembly that includes a third gas passage for introducing a second process gas into a fourth gas passage that introduces the second process gas into the processing chamber. The first and second gas distribution assemblies are each adapted to be coupled to at least one chamber wall of the processing chamber. The first gas passage is shaped as a first ring positioned within the processing chamber above the second gas passage that is shaped as a second ring positioned within the processing chamber. The gas distribution assemblies may be designed to have complementary characteristic radial film growth rate profiles.Type: GrantFiled: October 11, 2012Date of Patent: April 5, 2016Assignee: Applied Materials, Inc.Inventors: Tuoh-Bin Ng, Yuriy Melnik, Lily L Pang, Eda Tuncel, Lu Chen, Son T Nguyen
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Patent number: 9196795Abstract: Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described.Type: GrantFiled: June 25, 2014Date of Patent: November 24, 2015Assignee: Applied Materials, Inc.Inventors: Jie Su, Tuoh-Bin Ng, Olga Kryliouk, Sang Won Kang, Jie Cui
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Publication number: 20140367696Abstract: Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described.Type: ApplicationFiled: June 25, 2014Publication date: December 18, 2014Inventors: Jie Su, Tuoh-Bin Ng, Olga Kryliouk, Sang Won Kang, Jie Cui