Patents by Inventor Tuomas Heikkilä

Tuomas Heikkilä has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10897196
    Abstract: An arrangement involving printed conductive traces includes at least a voltage source (Vsupply) and at least one target component, preferably a light-emitting component such as an LED. The arrangement is adapted to produce a current-controlled voltage (VOUT2, Vout) originating from the voltage source, the current-controlled voltage being coupled to the at least one target component, wherein said voltage is dependent on the current (IR,LED, ILED) that is being passed through the target component and said voltage is adaptable to a varying resistance of the arrangement and its features.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: January 19, 2021
    Assignee: TACTOTEK OY
    Inventors: Miikka Kärnä, Tuomas Heikkilä
  • Publication number: 20200083806
    Abstract: An arrangement involving printed conductive traces includes at least a voltage source (Vsupply) and at least one target component, preferably a light-emitting component such as an LED. The arrangement is adapted to produce a current-controlled voltage (VOUT2, Vout) originating from the voltage source, the current-controlled voltage being coupled to the at least one target component, wherein said voltage is dependent on the current (IR,LED, ILED) that is being passed through the target component and said voltage is adaptable to a varying resistance of the arrangement and its features.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Miikka KÄRNÄ, Tuomas HEIKKILÄ
  • Patent number: 10491115
    Abstract: An arrangement involving printed conductive traces, the arrangement including at least a voltage source (Vsupply) and at least one target component, preferably a light-emitting component such as an LED. The arrangement is adapted to produce a current-controlled voltage (VOUT2, Vout) originating from the voltage source, the current-controlled voltage being coupled to the at least one target component, wherein said voltage is dependent on the current (IR,LED, ILED) that is being passed through the target component.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 26, 2019
    Assignee: TACTOTEK OY
    Inventors: Miikka Kärnä, Tuomas Heikkilä
  • Publication number: 20190190378
    Abstract: An arrangement involving printed conductive traces, the arrangement including at least a voltage source (Vsupply) and at least one target component, preferably a light-emitting component such as an LED. The arrangement is adapted to produce a current-controlled voltage (VOUT2, Vout) originating from the voltage source, the current-controlled voltage being coupled to the at least one target component, wherein said voltage is dependent on the current (IR,LED, LLED) that is being passed through the target component.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: Miikka KÄRNÄ, Tuomas HEIKKILÄ
  • Patent number: 10285261
    Abstract: An electrical node including a first substrate film defining a cavity and a first material layer arranged to at least partly fill the cavity, and to embed or at least partly cover at least one electrical element arranged into the cavity, wherein the first material layer includes elastic material to reduce thermal expansion related stresses between elements adjacent thereto.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 7, 2019
    Assignee: TACTOTEK OY
    Inventors: Tomi Simula, Vinski Bräysy, Mikko Heikkinen, Juha-Matti Hintikka, Juhani Harvela, Minna Pirkonen, Pasi Raappana, Tuomas Heikkilä, Jarmo Sääski
  • Patent number: 10225932
    Abstract: Interface arrangement comprising an electrical node type component for providing electrical or electromagnetic connection between an external system and a host structure of the interface arrangement. The interface arrangement comprising a first substrate film defining a cavity. A first material layer arranged to at least partly fill the cavity and to embed or at least partly cover at least one electrical element at least partly arranged into the cavity. The at least one electrical element comprises at least a converter element configured for adapting signals to be transferred between the external system and electronics of the host structure. A first connection element arranged at least partly into the cavity and configured for connecting to the external system. The first connection element is further at least functionally connected to the converter element. Related multilayer structures and methods of manufacture are presented.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: March 5, 2019
    Assignee: TACTOTEK OY
    Inventors: Tomi Simula, Vinski Bräysy, Mikko Heikkinen, Juha-Matti Hintikka, Minna Pirkonen, Pasi Raappana, Tuomas Heikkilä, Jarmo Sääski, Juhani Harvela
  • Patent number: 10194526
    Abstract: An electrical node, a method, an electrical assembly such as a node strip or sheet, a related multilayer structure, and a method of manufacture are presented. The electrical node comprises a first substrate film defining a cavity and a first material layer arranged to at least partly fill the cavity and to embed or at least partly cover at least one electrical element arranged into the cavity.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: January 29, 2019
    Assignee: TACTOTEK OY
    Inventors: Tomi Simula, Vinski Bräysy, Mikko Heikkinen, Juha-Matti Hintikka, Juhani Harvela, Minna Pirkonen, Pasi Raappana, Tuomas Heikkilä, Jarmo Sääski
  • Patent number: 10055530
    Abstract: An electronic arrangement for facilitating circuit layout design in connection with three-dimensional (3D) target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing 3D target design to be produced from a substrate, determining a mapping between locations of the 3D target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 21, 2018
    Assignee: TACTOTEK OY
    Inventors: Hasse Sinivaara, Tuomas Heikkilä, Antti Keränen
  • Patent number: 9990455
    Abstract: An electronic arrangement for facilitating circuit layout design in connection with three-dimensional (3D) target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing 3D target design to be produced from a substrate, determining a mapping between locations of the 3D target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 5, 2018
    Assignee: TACTOTEK OY
    Inventors: Hasse Sinivaara, Tuomas Heikkilä, Antti Keränen