Patents by Inventor Tushar Vidyadhar MANDREKAR

Tushar Vidyadhar MANDREKAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING REDUCED CONTACT RESISTANCE
    Publication number: 20220093749
    Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Tushar Vidyadhar MANDREKAR, Yuan-hui LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA
  • Method of fabricating a semiconductor device having reduced contact resistance
    Patent number: 11195923
    Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 7, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Gaurav Thareja, Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Tushar Vidyadhar Mandrekar, Andy Lo, Patricia M. Liu, Sanjay Natarajan, Saurabh Chopra
  • METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING REDUCED CONTACT RESISTANCE
    Publication number: 20200203490
    Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.
    Type: Application
    Filed: November 8, 2019
    Publication date: June 25, 2020
    Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Tushar Vidyadhar MANDREKAR, Andy LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA