Patents by Inventor Tushit Jain

Tushit Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11928411
    Abstract: Certain aspects of the present disclosure provide techniques for testing integrated circuit designs based on test cases selected using machine learning models. An example method generally includes receiving a plurality of test cases for an integrated circuit. An embedding data set is generated from the plurality of test cases. A respective embedding for a respective test case of the plurality of test cases generally includes a mapping of the respective test case into a multidimensional space. A plurality of test case clusters is generated based on a clustering model and the embedding data set. A plurality of critical test cases for testing the integrated circuit is selected based on the plurality of test case clusters. The integrated circuit is timed based on the plurality of critical test cases and a hard macro defining the integrated circuit.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: March 12, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Lindsey Makana Kostas, Santanu Pattanayak, Tushit Jain
  • Publication number: 20230102185
    Abstract: Certain aspects of the present disclosure provide techniques for testing integrated circuit designs based on test cases selected using machine learning models. An example method generally includes receiving a plurality of test cases for an integrated circuit. An embedding data set is generated from the plurality of test cases. A respective embedding for a respective test case of the plurality of test cases generally includes a mapping of the respective test case into a multidimensional space. A plurality of test case clusters is generated based on a clustering model and the embedding data set. A plurality of critical test cases for testing the integrated circuit is selected based on the plurality of test case clusters. The integrated circuit is timed based on the plurality of critical test cases and a hard macro defining the integrated circuit.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Lindsey Makana KOSTAS, Santanu PATTANAYAK, Tushit JAIN
  • Patent number: 10607572
    Abstract: Methods, systems, and devices for frequency synchronization and phase correction at a rendering device are described. One method may include receiving, from a display device (e.g., a head-mounted display (HMD) device), a vertical sync count and an indication of one or more frame repeats. The rendering device may estimate a vertical sync frequency based on the received vertical sync count, and determine a phase corresponding to a minimum frame repeat based on the indication of the one or more frame repeats. The rendering device may adjust a vertical sync frequency to the estimated vertical sync frequency and a phase to the determined phase. The rendering device may transmit one or more frames to the display device using the adjusted frequency and/or the adjusted phase.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Anand Prabhakar Satpute, Sandeep Kanakapura Lakshmikantha, Tushit Jain, Gwendolyn Denise Barriac, Ajit Venkat Rao
  • Publication number: 20190341004
    Abstract: Methods, systems, and devices for frequency synchronization and phase correction at a rendering device are described. One method may include receiving, from a display device (e.g., a head-mounted display (HMD) device), a vertical sync count and an indication of one or more frame repeats. The rendering device may estimate a vertical sync frequency based on the received vertical sync count, and determine a phase corresponding to a minimum frame repeat based on the indication of the one or more frame repeats. The rendering device may adjust a vertical sync frequency to the estimated vertical sync frequency and a phase to the determined phase. The rendering device may transmit one or more frames to the display device using the adjusted frequency and/or the adjusted phase.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 7, 2019
    Inventors: Anand Prabhakar Satpute, Sandeep Kanakapura Lakshmikantha, Tushit Jain, Gwendolyn Denise Barriac, Ajit Venkat Rao
  • Patent number: 10446119
    Abstract: Methods, systems, and devices for split rending of multiple graphic layers are described. An extended reality (XR) system may include a processing device that generates and renders multiple graphic layers and a display device that displays the graphic layers to create a virtual environment. The processing device may divide the multiple graphic layer into sets of graphic layers and composite each set into a composite layer for transmission to the display device over a respective stream. Each group of graphic layers may include graphic layers of the same type that are consecutively ordered with respect to their Z orders and that have similar frame rates.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 15, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Sandeep Kanakapura Lakshmikantha, Pawan Kumar Baheti, Ajit Venkat Rao, Tushit Jain