Abstract: A Peripheral Component Interconnect express (PCIe) Downstream Port Containment (DPC) System Management Interrupt (SMI) storm prevention system includes a Basic Input/Output System (BIOS) subsystem coupled to a first PCIe device. In response to an error being experienced in the first PCIe device and causing the first PCIe device to perform DPC operations, the BIOS subsystem receives a plurality of SMIs that are each configured to begin a System Management Mode (SMM). The BIOS subsystem tracks a number of the plurality of SMIs in a BIOS database and determines when the number of the plurality of SMIs has reached a DPC SMI storm threshold. In response to the number of the plurality of SMIs reaching the DPC SMI storm threshold, the BIOS subsystem prevents use of a link to the first PCIe device and prevents an operating system from performing recovery operations to recover the first PCIe device from the error.

Abstract: A Peripheral Component Interconnect express (PCIe) Downstream Port Containment (DPC) System Management Interrupt (SMI) storm prevention system includes a Basic Input/Output System (BIOS) subsystem coupled to a first PCIe device. In response to an error being experienced in the first PCIe device and causing the first PCIe device to perform DPC operations, the BIOS subsystem receives a plurality of SMIs that are each configured to begin a System Management Mode (SMM). The BIOS subsystem tracks a number of the plurality of SMIs in a BIOS database and determines when the number of the plurality of SMIs has reached a DPC SMI storm threshold. In response to the number of the plurality of SMIs reaching the DPC SMI storm threshold, the BIOS subsystem prevents use of a link to the first PCIe device and prevents an operating system from performing recovery operations to recover the first PCIe device from the error.

Abstract: A Peripheral Component Interconnect express (PCIe) Downstream Port Containment (DPC) System Management Interrupt (SMI) storm prevention system includes a Basic Input/Output System (BIOS) subsystem coupled to a first PCIe device. In response to an error being experienced in the first PCIe device and causing the first PCIe device to perform DPC operations, the BIOS subsystem receives a plurality of SMIs that are each configured to begin a System Management Mode (SMM). The BIOS subsystem tracks a number of the plurality of SMIs in a BIOS database and determines when the number of the plurality of SMIs has reached a DPC SMI storm threshold. In response to the number of the plurality of SMIs reaching the DPC SMI storm threshold, the BIOS subsystem prevents use of a link to the first PCIe device and prevents an operating system from performing recovery operations to recover the first PCIe device from the error.

Abstract: A PCIe device error handling system includes a BIOS subsystem coupled to a PCIe device and a BMC device. The BIOS subsystem identifies an error in the PCIe device and, in response, begins an SMM that suspends the performance of at least one workload in an operating system, and generates and transmits a PCIe device error information collection instruction associated with the PCIe device to the BMC device. Subsequent to transmitting the PCIe device error information collection instruction, the BIOS subsystem ends the SMM such that the performance of at least one workload is resumed in the operating system. In response to receiving the PCIe device error information collection instruction from the BIOS subsystem, the BMC device retrieves PCIe device error information from the PCIe device while the operating system performs the at least one workload, and stores the PCIe device error information.

Abstract: A method, an information handling system (IHS) and a memory mirroring system for operating a mirrored memory. The method includes detecting, via a memory controller, at least one uncorrectable data error (UCDE) in a first memory device. In response to detecting the at least one UCDE, a UCDE event counter is retrieved that tracks the number of UCDE events that have occurred and a UCDE event threshold is retrieved corresponding to a maximum number of allowed UCDE events. The method further includes determining if the UCDE event counter is greater than the UCDE event threshold and in response to determining that the UCDE event counter is not greater than the UCDE event threshold, continuing writing of data to the first memory device via a first memory channel and continuing writing of the data to a second memory device via a second memory channel to create a mirror of the data.

Abstract: Systems and methods for preventing system crashes due to memory link failure in memory mirroring mode in an information handling system (IHS). The IHS may include a first memory device, a second memory device, and an integrated memory controller (IMC). The IMC may issue write transactions to both the first and second memory devices and issue read transactions to the first memory device when the IMC is in memory mirroring mode. The IMC may transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device. The BIOS may perform a memory mirror failover process that may cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error.

Abstract: An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor to receive the interrupts, accumulate a count of the interrupts, and provide a first error indication when the count exceeds a first error threshold. The failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when the DIMM is newer than a first age threshold and has a second value when the DIMM is older than the first age threshold.

Abstract: An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. The failure predictor receives a first in time interrupt, suspends the accumulation of the count for a first duration of time in response to receiving the first in time interrupt, and resumes the accumulation of the count. In resuming the accumulation of the count, the failure predictor increments the count each time the predictor receives a first subsequent interrupt and decrements the count in accordance with an error leak rate.

Abstract: A method, an information handling system (IHS) and a memory mirroring system for operating a mirrored memory. The method includes detecting, via a memory controller, at least one uncorrectable data error (UCDE) in a first memory device. In response to detecting the at least one UCDE, a UCDE event counter is retrieved that tracks the number of UCDE events that have occurred and a UCDE event threshold is retrieved corresponding to a maximum number of allowed UCDE events. The method further includes determining if the UCDE event counter is greater than the UCDE event threshold and in response to determining that the UCDE event counter is not greater than the UCDE event threshold, continuing writing of data to the first memory device via a first memory channel and continuing writing of the data to a second memory device via a second memory channel to create a mirror of the data.

Abstract: Systems and methods for preventing system crashes due to memory link failure in memory mirroring mode in an information handling system (IHS). The IHS may include a first memory device, a second memory device, and an integrated memory controller (IMC). The IMC may issue write transactions to both the first and second memory devices and issue read transactions to the first memory device when the IMC is in memory mirroring mode. The IMC may transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device. The BIOS may perform a memory mirror failover process that may cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error.

Abstract: An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Abstract: An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Abstract: An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Abstract: An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Abstract: An apparatus and method are disclosed for reducing the amount of time to execute a boot sequence, such as a power-on self-test (POST) routine, by eliminating a scan for devices interfaced with a local bus associated with a computer system. A detection circuit interfaces with a card slot through the local bus and generates a status bit indicating whether the configuration of devices for the computer system changed after completion of a first boot sequence. A processor interfaces with the local bus and reads the status bit during a second boot sequence. If the status bit indicates that the computer system device configuration remains the same, the processor eliminates the scan for devices interfaced with the computer system.

Abstract: A method and system for displaying information at a remote display device from an information processing system that lacks video display components causes the information processing system to initiate system memory to store video information despite the lack of video components, thus allowing applications to write display information to the system memory and allowing the information handling system to re-direct the display information to the remote display. For instance, the information handling system BIOS includes a video function module that detects a lack of video display components, determines that the information handling system is a headless server, and initiates system memory to store video information. A remote display module associated with the BIOS monitors the system memory and re-directs detected display information stored in the system memory to a remote information handling system that displays the information.

Abstract: A method for handling system management interrupts in multiprocessors systems is provided. After the processors of the system enter system management mode, one of the processors of the system is designated to handle the system management interrupt. The processor designated to handle the system management interrupt scans a memory location that includes a memory space associated with the saved contents of the processor registers of each processor. After locating a SMI signature in one of the memory spaces associated with the respective processors of the system, the SMI handler of the processor designated to handle the system management interrupts, retrieves any necessary parameters for the system management interrupt from the memory space associated with the SMI signature, thereby allowing a processor to cause the issuance a SMI, to pass a set of parameters for the software SMI, and to permit a second processor to receive the parameters and handle the software SMI.