Abstract: A semiconductor memory device includes two subcircuits each including a memory circuit, a semiconductor circuit, and a logical circuit. Connection pads are divided into only two parallel rows located along the outer periphery of the semiconductor memory device. Each of the pads may include a probe region against which a probe is pressed for testing the semiconductor memory circuit, and a wire region to which a wire is connected upon packaging.

Abstract: A semiconductor memory device is constituted such that, when a first wiring layer provides a bit line of a first common complementary data line pair and a third wiring layer provides a bit line of a second common complementary data line pair, a second wiring layer makes an overlapped area between the bit line and the bit bar line of the second common complementary dada line pair equal to the bit line of the first common complementary data line pair and also an overlapped area between the bit line and the bit bar line of the first common complementary data line pair equal to the bit line of the second common complementary data line pair.