Patents by Inventor Twan Bearda

Twan Bearda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10892377
    Abstract: Example embodiments relate to selective deposition for interdigitated patterns in solar cells. One embodiment includes a method for creating an interdigitated pattern for a solar cell. The method includes providing a substrate of the solar cell. A surface of the substrate includes one or more exposed regions and one or more regions covered by a patterned first passivation layer stack protected by a hard mask. The method also includes selectively depositing a second passivation layer stack that includes at least a first layer of amorphous silicon (a-Si) on the one or more exposed regions such that the first passivation layer stack and the second passivation layer stack form the interdigitated pattern. Selectively depositing the second passivation layer stack includes adding a sublayer of the first layer on the hard mask, etching the added sublayer on the hard mask, and cleaning a surface of the remaining added sublayer.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: January 12, 2021
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Menglei Xu, Twan Bearda, Hariharsudan Sivaramakrishnan Radhakrishnan, Jef Poortmans
  • Publication number: 20200091368
    Abstract: Example embodiments relate to selective deposition for interdigitated patterns in solar cells. One embodiment includes a method for creating an interdigitated pattern for a solar cell. The method includes providing a substrate of the solar cell. A surface of the substrate includes one or more exposed regions and one or more regions covered by a patterned first passivation layer stack protected by a hard mask. The method also includes selectively depositing a second passivation layer stack that includes at least a first layer of amorphous silicon (a-Si) on the one or more exposed regions such that the first passivation layer stack and the second passivation layer stack form the interdigitated pattern. Selectively depositing the second passivation layer stack includes adding a sublayer of the first layer on the hard mask, etching the added sublayer on the hard mask, and cleaning a surface of the remaining added sublayer.
    Type: Application
    Filed: August 14, 2019
    Publication date: March 19, 2020
    Inventors: Menglei Xu, Twan Bearda, Hariharsudan Sivaramakrishnan Radhakrishnan, Jef Poortmans
  • Patent number: 10326031
    Abstract: Methods of patterning an amorphous semiconductor layer according to a predetermined pattern via laser ablation with a pulsed laser having a laser wavelength are disclosed. In one aspect, a method may include providing the amorphous semiconductor layer on a substrate, providing a distributed Bragg reflector on the amorphous semiconductor layer, wherein the distributed Bragg reflector is reflective at the laser wavelength, providing an absorbing layer on the distributed Bragg reflector, wherein the absorbing layer is absorptive at the laser wavelength, patterning the absorbing layer by laser ablation, in accordance with the predetermined pattern, patterning the distributed Bragg reflector by performing an etching step using the patterned absorbing layer as an etch mask, and etching the amorphous semiconductor layer using the patterned distributed Bragg reflector as an etch mask.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 18, 2019
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Menglei Xu, Miha Filipic, Twan Bearda
  • Publication number: 20180122963
    Abstract: Methods of patterning an amorphous semiconductor layer according to a predetermined pattern via laser ablation with a pulsed laser having a laser wavelength are disclosed. In one aspect, a method may include providing the amorphous semiconductor layer on a substrate, providing a distributed Bragg reflector on the amorphous semiconductor layer, wherein the distributed Bragg reflector is reflective at the laser wavelength, providing an absorbing layer on the distributed Bragg reflector, wherein the absorbing layer is absorptive at the laser wavelength, patterning the absorbing layer by laser ablation, in accordance with the predetermined pattern, patterning the distributed Bragg reflector by performing an etching step using the patterned absorbing layer as an etch mask, and etching the amorphous semiconductor layer using the patterned distributed Bragg reflector as an etch mask.
    Type: Application
    Filed: November 3, 2017
    Publication date: May 3, 2018
    Inventors: Menglei Xu, Miha Filipic, Twan Bearda
  • Patent number: 9123859
    Abstract: A method for module-level processing of photovoltaic cells is provided. The method includes: bonding at least one crystalline silicon photovoltaic substrate to a carrier by means of an adhesive layer, thereby leaving part of the adhesive layer uncovered; after bonding, exposing the uncovered part of the adhesive layer and the at least one crystalline silicon photovoltaic substrate to a plasma; and removing a surface portion of the at least one crystalline photovoltaic substrate. The method may further include performing an annealing step of the adhesive before bonding the at least one photovoltaic substrate to the carrier, and performing an outgassing step of the adhesive after bonding the at least one photovoltaic substrate to the carrier. The method may further include module-level rear side processing of the at least one crystalline silicon photovoltaic substrate to make a photovoltaic module.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: September 1, 2015
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Stefano Granata, Twan Bearda
  • Publication number: 20150111335
    Abstract: A method for module-level processing of photovoltaic cells is provided. The method includes: bonding at least one crystalline silicon photovoltaic substrate to a carrier by means of an adhesive layer, thereby leaving part of the adhesive layer uncovered; after bonding, exposing the uncovered part of the adhesive layer and the at least one crystalline silicon photovoltaic substrate to a plasma; and removing a surface portion of the at least one crystalline photovoltaic substrate. The method may further include performing an annealing step of the adhesive before bonding the at least one photovoltaic substrate to the carrier, and performing an outgassing step of the adhesive after bonding the at least one photovoltaic substrate to the carrier. The method may further include module-level rear side processing of the at least one crystalline silicon photovoltaic substrate to make a photovoltaic module.
    Type: Application
    Filed: September 8, 2014
    Publication date: April 23, 2015
    Applicants: KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D, IMEC VZW
    Inventors: Stefano Granata, Twan Bearda
  • Publication number: 20110308603
    Abstract: A method of passivating a silicon surface is disclosed. In one aspect, the method includes cleaning the silicon surface by subjecting the silicon surface to a sequence of steps wherein the final step is a chemical oxidation step resulting in a hydrophilic silicon surface. The method may also include drying the cleaned silicon surface using an advanced drying technique, and/or depositing an oxide layer on the silicon surface.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 22, 2011
    Applicants: Katholieke Universiteit Leuven, IMEC
    Inventors: Bart Vermang, Aude Rothschild, Twan Bearda
  • Patent number: 7060587
    Abstract: A method for forming macropores in a substrate is disclosed. On a substrate a pattern of submicron features is formed. This pattern is covered with a layer, which is preferably selectively removable with respect to the substrate and the submicron features. This cover layer is removed until the submicron features are exposed. The submicron features are then etched selectively to the cover layer, thereby creating a pattern of submicron openings in this cover layer. The patterned cover layer is used as a hardmask to etch macropores in the substrate.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: June 13, 2006
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Twan Bearda, Eddy Kunnen
  • Publication number: 20050189318
    Abstract: A method for forming macropores in a substrate is disclosed. On a substrate a pattern of submicron features is formed. This pattern is covered with a layer, which is preferably selectively removable with respect to the substrate and the submicron features. This cover layer is removed until the submicron features are exposed. The submicron features are then etched selectively to the cover layer, thereby creating a pattern of submicron openings in this cover layer. The patterned cover layer is used as a hardmask to etch macropores in the substrate.
    Type: Application
    Filed: January 28, 2005
    Publication date: September 1, 2005
    Inventors: Twan Bearda, Eddy Kunnen