Patents by Inventor Twila J. Reeves

Twila J. Reeves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5474958
    Abstract: A wire bondable plastic encapsulated semiconductor device (58) having no die supporting surface can be manufactured. In one embodiment, a semiconductor die (22) and a plurality of conductors (12) extending toward the periphery of the die are provided. The die is rigidly held in place on a workholder (60) with a vacuum (62) for the wire bonding process. Wire bonds (26) electrically connect the die to the conductors. The wire bonded die is then placed inside a mold cavity (64), and a resin encapsulated is transferred into the cavity under elevated temperature and pressure to form package body (70) around the die, the wire bonds and a portion of the conductors. Before the package body is formed, the die is supported solely by the the rigidity of the wire bonds since there is no die supporting surface connected to the conductors.
    Type: Grant
    Filed: May 4, 1993
    Date of Patent: December 12, 1995
    Assignee: Motorola, Inc.
    Inventors: Frank Djennas, Victor K. Nomi, John R. Pastore, Twila J. Reeves, Les Postlethwait
  • Patent number: 5467252
    Abstract: Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: November 14, 1995
    Assignee: Motorola, Inc.
    Inventors: Victor Nomi, John R. Pastore, Twila J. Reeves
  • Patent number: RE36773
    Abstract: Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: July 11, 2000
    Assignee: Motorola, Inc.
    Inventors: Victor K. Nomi, John R. Pastore, Twila J. Reeves