Abstract: Systems and methods for performing matrix operations using a photonic processor are provided. The photonic processor includes encoders configured to encode a numerical value into an optical signal and optical multiplication devices configured to output an electrical signal proportional to a product of one or more encoded values. The optical multiplication devices include a first input waveguide, a second input waveguide, a coupler circuit coupled to the first input waveguide and the second input waveguide, a first detector and a second detector coupled to the coupler circuit, and a circuit coupled to the first detector and second detector and configured to output a current that is proportional to a product of a first input value and a second input value.

Abstract: Aspects of the present disclosure provide an aligned storage strategy for stripes within a long vector for a vector processor, such that the extra computation needed to track strides between input stripes and output stripes may be eliminated. As a result, the stripe locations are located in a more predictable memory access pattern such that memory access bandwidth may be improved and the tendency for memory error may be reduced.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Systems and methods for performing matrix operations using a photonic processor are provided. The photonic processor includes encoders configured to encode a numerical value into an optical signal and optical multiplication devices configured to output an electrical signal proportional to a product of one or more encoded values. The optical multiplication devices include a first input waveguide, a second input waveguide, a coupler circuit coupled to the first input waveguide and the second input waveguide, a first detector and a second detector coupled to the coupler circuit, and a circuit coupled to the first detector and second detector and configured to output a current that is proportional to a product of a first input value and a second input value.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Methods and systems for training neural networks using low-bitwidth accelerators are described. The methods described herein use moment-penalization functions. For example, a method comprises producing a modified data set by training a neural network using a moment-penalization function and the data set. The moment-penalization function is configured to penalize a moment associated with the neural network. Training the neural network in turn comprises quantizing the data set to obtain a fixed-point data set so that the fixed-point data set represents the data set in a fixed-point representation, and passing the fixed-point data set through an analog accelerator. The inventors have recognized that training a neural network using a modified objective function augments the accuracy and robustness of the neural network notwithstanding the use of low-bitwidth accelerators.

Abstract: Aspects of the present disclosure provide an aligned storage strategy for stripes within a long vector for a vector processor, such that the extra computation needed to track strides between input stripes and output stripes may be eliminated. As a result, the stripe locations are located in a more predictable memory access pattern such that memory access bandwidth may be improved and the tendency for memory error may be reduced.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: A computer-implemented method for generating executable code for a hardware architecture comprising a primary functional unit and a non-primary functional unit is provided. Source code is translated into representative primary functional unit instructions for a representative primary functional unit in a representative processor architecture model wherein functionality of the non-primary functional unit in the hardware architecture is modeled by the representative primary functional unit in the representative processor architecture model. The representative primary functional unit instructions are transformed into executable non-primary functional unit instructions for the non-primary functional unit in the hardware architecture.

Abstract: An apparatus and computer program product for generating executable code for a hardware architecture comprising a primary functional unit and a non-primary functional unit are provided. Source code is translated into representative primary functional unit instructions for a representative primary functional unit in a representative processor architecture model wherein functionality of the non-primary functional unit in the hardware architecture is modeled by the representative primary functional unit in the representative processor architecture model. The representative primary functional unit instructions are transformed into executable non-primary functional unit instructions for the non-primary functional unit in the hardware architecture.

Abstract: A computer-implemented method for generating executable code for a hardware architecture comprising a primary functional unit and a non-primary functional unit is provided. Source code is translated into representative primary functional unit instructions for a representative primary functional unit in a representative processor architecture model wherein functionality of the non-primary functional unit in the hardware architecture is modeled by the representative primary functional unit in the representative processor architecture model. The representative primary functional unit instructions are transformed into executable non-primary functional unit instructions for the non-primary functional unit in the hardware architecture.

Abstract: An apparatus and computer program product for generating executable code for a hardware architecture comprising a primary functional unit and a non-primary functional unit are provided. Source code is translated into representative primary functional unit instructions for a representative primary functional unit in a representative processor architecture model wherein functionality of the non-primary functional unit in the hardware architecture is modeled by the representative primary functional unit in the representative processor architecture model. The representative primary functional unit instructions are transformed into executable non-primary functional unit instructions for the non-primary functional unit in the hardware architecture.